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Benchmark Data

Important

Performance varies by use, configuration and other factors. Learn more at https://intel.com/PerformanceIndex.

Performance results are based on testing as of dates shown in configurations and may not reflect all publicly available updates. See configuration disclosure for details. No product or component can be absolutely secure.

Your costs and results may vary.

Intel technologies may require enabled hardware, software or service activation.

The following section is applicable to:

Benchmark Platforms

Vecow Core i7-8665UE

Unless otherwise stated, results obtained for the Core i7-8665UE were performed on the following system:

Manufacturer	Vecow
MPN	SPC-5200
Processor	Core i7-8665UE 1.7GHz to 4.4GHz quad core 15W TDP
Memory	32 GB DDR4
OS	ECI base-poky

Maxtang Core i7-8665U

Unless otherwise stated, results obtained for the Core i7-8665U were performed on the following system:

Manufacturer	Maxtang
MPN	AX8665U-A3
Processor	Core i7-8665U 1.9GHz to 4.8GHz quad core 15W TDP
Memory	8 GB DDR4
OS	ECI base-poky

Vecow Core i7-1185G7E

Unless otherwise stated, results obtained for the Core i7-1185G7E were performed on the following system:

Manufacturer	Vecow
MPN	SPC-7100
Processor	Core i7-1185G7E 1.8GHz to 4.4GHz quad core 15W TDP
Memory	16 GB DDR4
OS	ECI base-poky

Karbon 700 Core i7-9700TE

Unless otherwise stated, results obtained for the Core i7-9700TE were performed on the following system:

Manufacturer	OnLogic
MPN	K700-SE
Processor	Core i7-9700TE 1.8GHz to 3.8GHz quad core 35W TDP
Memory	32 GB DDR4
OS	ECI base-poky

Tiger Lake Reference Validation Platform Core i5-1145GRE

Unless otherwise stated, results obtained for the Core i5-1145GRE were performed on the following system:

Important

** The Tiger Lake Reference Validation Platform (TGL-RVP) is not a commercially available product. The TGR silicon used in ECI validation was B0 stepping with TSN enabled. Results obtained using production silicon may differ!

Manufacturer	N/A
MPN	N/A
Processor	Core i7-1185GRE 1.5GHz to 4.1GHz quad core 15W TDP
Memory	16 GB DDR4
OS	ECI base-poky

Elkhart Lake Customer Reference Board Atom x6425RE

Unless otherwise stated, results obtained for the Atom x6425RE were performed on the following system:

Important

** The Elkhart Lake Customer Reference Board (EHL-CRB) is not a commercially available product. The EHL silicon used in ECI validation was B0 stepping with FuSa enabled. Results obtained using production silicon may differ!

Manufacturer	N/A
MPN	N/A
Processor	Atom x6245RE 1.9GHz 15W TDP
Memory	8 GB DDR4
OS	ECI base-poky

Cyclictest Results

See also

See section Cyclictest Workload for more information about this benchmark.

The following configuration was used:

• One thread per core

• Use clock_nanosleep instead of posix interval timers

• Set number of threads to the number of cpus and same priority of all threads

• Priority = 99

• Timer interval on core 0: 100[us]

• Interval increment for each core: 20[us]

• Number of loops (on core 0): 30000

Vecow Core i7-8665UE - RT Benchmark

Click to toggle the results

# ==============================================================================
#   Test case (1/6): rt_bmark.intlat.no_stress
# ..............................................................................
# No stress requested
# Starting cyclictest
#   Command          : /opt/benchmarking/rt-tests/cyclictest -S -p 99 -q -i 100 -d 20 -l 30000
#   Number of cycles : 960000 (32 sets of 30000 cycles)
#   Exec. time (est) : 0:01:36
# Hung task detection not supported
#   (File /proc/sys/kernel/hung_task_timeout_secs not found)
# 23:28:15: Start of execution
# 23:28:18:  1/32: min:    2 avg:   2.3 max:   26
# 23:28:21:  2/32: min:    2 avg:   2.0 max:   15
# 23:28:24:  3/32: min:    2 avg:   2.0 max:   16
# 23:28:27:  4/32: min:    2 avg:   2.0 max:    9
# 23:28:31:  5/32: min:    2 avg:   2.2 max:    6
# 23:28:34:  6/32: min:    2 avg:   2.0 max:   12
# 23:28:37:  7/32: min:    2 avg:   2.0 max:    7
# 23:28:40:  8/32: min:    2 avg:   2.2 max:   14
# 23:28:43:  9/32: min:    2 avg:   2.0 max:   11
# 23:28:46: 10/32: min:    2 avg:   2.2 max:   16
# 23:28:49: 11/32: min:    2 avg:   2.0 max:    9
# 23:28:52: 12/32: min:    2 avg:   2.0 max:   11
# 23:28:55: 13/32: min:    2 avg:   2.2 max:   11
# 23:28:58: 14/32: min:    2 avg:   2.0 max:   12
# 23:29:01: 15/32: min:    2 avg:   2.5 max:    7
# 23:29:04: 16/32: min:    2 avg:   2.0 max:   10
# 23:29:07: 17/32: min:    2 avg:   2.2 max:   14
# 23:29:10: 18/32: min:    2 avg:   2.3 max:   14
# 23:29:14: 19/32: min:    2 avg:   2.2 max:    9
# 23:29:17: 20/32: min:    2 avg:   2.0 max:   10
# 23:29:20: 21/32: min:    2 avg:   2.2 max:   14
# 23:29:23: 22/32: min:    2 avg:   2.2 max:   13
# 23:29:26: 23/32: min:    2 avg:   2.2 max:    7
# 23:29:29: 24/32: min:    2 avg:   2.2 max:   12
# 23:29:32: 25/32: min:    2 avg:   2.5 max:   11
# 23:29:35: 26/32: min:    2 avg:   2.0 max:    9
# 23:29:38: 27/32: min:    2 avg:   2.2 max:   14
# 23:29:41: 28/32: min:    2 avg:   2.0 max:   14
# 23:29:44: 29/32: min:    2 avg:   2.0 max:   14
# 23:29:47: 30/32: min:    2 avg:   2.0 max:   13
# 23:29:50: 31/32: min:    1 avg:   2.0 max:    8
# 23:29:53: 32/32: min:    2 avg:   2.0 max:   10
# 23:29:53: Cyclictest completed. Actual execution time:0:01:38
# Min: 1 us
# Avg: 2.1 us
# Max: 26 us
# Max list: [6, 10, 12, 14, 14, 26]
# PASS

rt_bmark.intlat.no_stress [Min/us,Avg/us,Max/us]:
1,2.1,26
PASS: rt_bmark.intlat.no_stress

# ==============================================================================
#   Test case (2/6): rt_bmark.intlat.cpu
# ..............................................................................
# Starting stress(cpu)
#   Command: 'stress -c 4'
# Starting cyclictest
#   Command          : /opt/benchmarking/rt-tests/cyclictest -S -p 99 -q -i 100 -d 20 -l 30000
#   Number of cycles : 960000 (32 sets of 30000 cycles)
#   Exec. time (est) : 0:01:36
# 23:29:53: Start of execution
stress: info: [2514] dispatching hogs: 4 cpu, 0 io, 0 vm, 0 hdd
# 23:29:57:  1/32: min:    2 avg:   2.0 max:   41
# 23:30:00:  2/32: min:    2 avg:   2.3 max:   10
# 23:30:03:  3/32: min:    2 avg:   2.0 max:    7
# 23:30:06:  4/32: min:    2 avg:   2.0 max:    9
# 23:30:09:  5/32: min:    2 avg:   2.3 max:   11
# 23:30:12:  6/32: min:    2 avg:   2.0 max:   13
# 23:30:15:  7/32: min:    2 avg:   2.3 max:    7
# 23:30:18:  8/32: min:    2 avg:   2.0 max:   14
# 23:30:21:  9/32: min:    2 avg:   2.0 max:    8
# 23:30:25: 10/32: min:    2 avg:   2.0 max:    8
# 23:30:28: 11/32: min:    2 avg:   2.0 max:   14
# 23:30:31: 12/32: min:    2 avg:   2.0 max:    9
# 23:30:34: 13/32: min:    2 avg:   2.0 max:   14
# 23:30:37: 14/32: min:    2 avg:   2.0 max:    6
# 23:30:40: 15/32: min:    2 avg:   2.3 max:   12
# 23:30:43: 16/32: min:    2 avg:   2.0 max:    9
# 23:30:46: 17/32: min:    2 avg:   2.0 max:   12
# 23:30:49: 18/32: min:    2 avg:   2.0 max:   11
# 23:30:53: 19/32: min:    2 avg:   2.0 max:   15
# 23:30:56: 20/32: min:    2 avg:   2.3 max:   12
# 23:30:59: 21/32: min:    2 avg:   2.3 max:   11
# 23:31:02: 22/32: min:    2 avg:   2.0 max:   14
# 23:31:05: 23/32: min:    2 avg:   2.0 max:   12
# 23:31:08: 24/32: min:    2 avg:   2.0 max:   10
# 23:31:11: 25/32: min:    2 avg:   2.0 max:   16
# 23:31:14: 26/32: min:    2 avg:   2.3 max:   15
# 23:31:17: 27/32: min:    2 avg:   2.0 max:   13
# 23:31:21: 28/32: min:    2 avg:   2.3 max:    5
# 23:31:24: 29/32: min:    2 avg:   2.0 max:   15
# 23:31:27: 30/32: min:    2 avg:   2.0 max:    8
# 23:31:30: 31/32: min:    2 avg:   2.0 max:   10
# 23:31:33: 32/32: min:    2 avg:   2.0 max:    9
# 23:31:33: Cyclictest completed. Actual execution time:0:01:39
# Terminated stress
# Min: 2 us
# Avg: 2.1 us
# Max: 41 us
# Max list: [5, 8, 14, 14, 16, 41]
# PASS

rt_bmark.intlat.cpu [Min/us,Avg/us,Max/us]:
2,2.1,41
PASS: rt_bmark.intlat.cpu

# ==============================================================================
#   Test case (3/6): rt_bmark.intlat.hdd
# ..............................................................................
# Starting stress(hdd)
#   Command: 'stress -d 4 --hdd-bytes 20M'
# Starting cyclictest
#   Command          : /opt/benchmarking/rt-tests/cyclictest -S -p 99 -q -i 100 -d 20 -l 30000
#   Number of cycles : 960000 (32 sets of 30000 cycles)
#   Exec. time (est) : 0:01:36
# 23:31:33: Start of execution
stress: info: [2679] dispatching hogs: 0 cpu, 0 io, 0 vm, 4 hdd
# 23:31:36:  1/32: min:    2 avg:   3.2 max:   52
# 23:31:39:  2/32: min:    2 avg:   3.2 max:   48
# 23:31:42:  3/32: min:    2 avg:   3.2 max:   54
# 23:31:45:  4/32: min:    2 avg:   3.2 max:   59
# 23:31:48:  5/32: min:    2 avg:   3.2 max:   42
# 23:31:52:  6/32: min:    2 avg:   3.5 max:   26
# 23:31:55:  7/32: min:    2 avg:   3.0 max:   26
# 23:31:58:  8/32: min:    2 avg:   3.3 max:   28
# 23:32:01:  9/32: min:    2 avg:   3.5 max:   27
# 23:32:04: 10/32: min:    2 avg:   3.2 max:   31
# 23:32:07: 11/32: min:    2 avg:   3.5 max:   33
# 23:32:10: 12/32: min:    2 avg:   3.2 max:   40
# 23:32:13: 13/32: min:    2 avg:   3.2 max:   42
# 23:32:17: 14/32: min:    2 avg:   3.5 max:   53
# 23:32:20: 15/32: min:    2 avg:   3.2 max:   58
# 23:32:23: 16/32: min:    2 avg:   3.2 max:   43
# 23:32:26: 17/32: min:    2 avg:   3.5 max:   52
# 23:32:29: 18/32: min:    2 avg:   3.2 max:   34
# 23:32:32: 19/32: min:    2 avg:   3.5 max:   38
# 23:32:35: 20/32: min:    2 avg:   3.2 max:   27
# 23:32:38: 21/32: min:    2 avg:   3.2 max:   40
# 23:32:41: 22/32: min:    2 avg:   3.2 max:   25
# 23:32:45: 23/32: min:    2 avg:   3.2 max:   32
# 23:32:48: 24/32: min:    2 avg:   3.5 max:   31
# 23:32:51: 25/32: min:    2 avg:   3.5 max:   32
# 23:32:54: 26/32: min:    2 avg:   3.2 max:   29
# 23:32:57: 27/32: min:    2 avg:   3.5 max:   38
# 23:33:00: 28/32: min:    2 avg:   3.0 max:   27
# 23:33:03: 29/32: min:    2 avg:   3.2 max:   40
# 23:33:06: 30/32: min:    2 avg:   3.3 max:   28
# 23:33:09: 31/32: min:    2 avg:   3.2 max:   26
# 23:33:13: 32/32: min:    2 avg:   3.2 max:   32
# 23:33:13: Cyclictest completed. Actual execution time:0:01:40
# Terminated stress
# Min: 2 us
# Avg: 3.3 us
# Max: 59 us
# Max list: [25, 28, 38, 40, 52, 59]
# PASS

rt_bmark.intlat.hdd [Min/us,Avg/us,Max/us]:
2,3.3,59
PASS: rt_bmark.intlat.hdd

# ==============================================================================
#   Test case (4/6): rt_bmark.intlat.io
# ..............................................................................
# Starting stress(io)
#   Command: 'stress -i 4'
# Starting cyclictest
#   Command          : /opt/benchmarking/rt-tests/cyclictest -S -p 99 -q -i 100 -d 20 -l 30000
#   Number of cycles : 960000 (32 sets of 30000 cycles)
#   Exec. time (est) : 0:01:36
# 23:33:13: Start of execution
stress: info: [2844] dispatching hogs: 0 cpu, 4 io, 0 vm, 0 hdd
# 23:33:16:  1/32: min:    2 avg:   2.0 max:   46
# 23:33:19:  2/32: min:    2 avg:   2.2 max:   11
# 23:33:22:  3/32: min:    2 avg:   2.5 max:   11
# 23:33:25:  4/32: min:    2 avg:   2.2 max:   12
# 23:33:28:  5/32: min:    2 avg:   2.2 max:   12
# 23:33:31:  6/32: min:    1 avg:   2.2 max:   11
# 23:33:34:  7/32: min:    2 avg:   2.2 max:   15
# 23:33:37:  8/32: min:    2 avg:   2.5 max:   14
# 23:33:40:  9/32: min:    2 avg:   2.2 max:   14
# 23:33:43: 10/32: min:    2 avg:   2.5 max:    9
# 23:33:46: 11/32: min:    2 avg:   2.5 max:   14
# 23:33:49: 12/32: min:    2 avg:   2.2 max:   14
# 23:33:52: 13/32: min:    2 avg:   2.2 max:   13
# 23:33:56: 14/32: min:    2 avg:   2.2 max:   10
# 23:33:59: 15/32: min:    2 avg:   2.2 max:   13
# 23:34:02: 16/32: min:    1 avg:   2.2 max:   13
# 23:34:05: 17/32: min:    2 avg:   2.2 max:   14
# 23:34:08: 18/32: min:    2 avg:   2.5 max:   15
# 23:34:11: 19/32: min:    2 avg:   2.2 max:   10
# 23:34:14: 20/32: min:    2 avg:   2.2 max:   14
# 23:34:17: 21/32: min:    2 avg:   2.2 max:   10
# 23:34:20: 22/32: min:    1 avg:   2.2 max:    9
# 23:34:23: 23/32: min:    2 avg:   2.5 max:   16
# 23:34:26: 24/32: min:    2 avg:   2.5 max:   10
# 23:34:29: 25/32: min:    2 avg:   2.2 max:   12
# 23:34:32: 26/32: min:    2 avg:   2.2 max:   10
# 23:34:35: 27/32: min:    2 avg:   2.8 max:   11
# 23:34:39: 28/32: min:    2 avg:   2.5 max:    8
# 23:34:42: 29/32: min:    1 avg:   2.2 max:   10
# 23:34:45: 30/32: min:    2 avg:   2.2 max:   10
# 23:34:48: 31/32: min:    2 avg:   2.2 max:   12
# 23:34:51: 32/32: min:    2 avg:   2.2 max:    9
# 23:34:51: Cyclictest completed. Actual execution time:0:01:38
# Terminated stress
# Min: 1 us
# Avg: 2.3 us
# Max: 46 us
# Max list: [8, 10, 12, 12, 16, 46]
# PASS

rt_bmark.intlat.io [Min/us,Avg/us,Max/us]:
1,2.3,46
PASS: rt_bmark.intlat.io

# ==============================================================================
#   Test case (5/6): rt_bmark.intlat.vm
# ..............................................................................
# Starting stress(vm)
#   Command: 'stress -m 4 --vm-bytes 10M'
# Starting cyclictest
#   Command          : /opt/benchmarking/rt-tests/cyclictest -S -p 99 -q -i 100 -d 20 -l 30000
#   Number of cycles : 960000 (32 sets of 30000 cycles)
#   Exec. time (est) : 0:01:36
# 23:34:51: Start of execution
stress: info: [3010] dispatching hogs: 0 cpu, 0 io, 4 vm, 0 hdd
# 23:34:54:  1/32: min:    2 avg:   4.5 max:   30
# 23:34:57:  2/32: min:    2 avg:   4.3 max:   28
# 23:35:00:  3/32: min:    2 avg:   4.3 max:   31
# 23:35:03:  4/32: min:    2 avg:   4.0 max:   29
# 23:35:06:  5/32: min:    2 avg:   4.0 max:   27
# 23:35:09:  6/32: min:    2 avg:   4.3 max:   30
# 23:35:13:  7/32: min:    2 avg:   4.3 max:   29
# 23:35:16:  8/32: min:    2 avg:   4.3 max:   29
# 23:35:19:  9/32: min:    2 avg:   4.3 max:   28
# 23:35:22: 10/32: min:    2 avg:   4.3 max:   28
# 23:35:25: 11/32: min:    2 avg:   4.5 max:   28
# 23:35:28: 12/32: min:    2 avg:   4.5 max:   29
# 23:35:31: 13/32: min:    2 avg:   3.7 max:   29
# 23:35:34: 14/32: min:    2 avg:   4.3 max:   32
# 23:35:37: 15/32: min:    2 avg:   4.0 max:   29
# 23:35:40: 16/32: min:    2 avg:   4.3 max:   32
# 23:35:44: 17/32: min:    2 avg:   4.0 max:   26
# 23:35:47: 18/32: min:    2 avg:   4.5 max:   32
# 23:35:50: 19/32: min:    2 avg:   4.5 max:   28
# 23:35:53: 20/32: min:    2 avg:   4.0 max:   29
# 23:35:56: 21/32: min:    2 avg:   4.3 max:   29
# 23:35:59: 22/32: min:    2 avg:   4.0 max:   26
# 23:36:02: 23/32: min:    2 avg:   4.3 max:   28
# 23:36:05: 24/32: min:    2 avg:   4.2 max:   29
# 23:36:08: 25/32: min:    2 avg:   4.0 max:   25
# 23:36:12: 26/32: min:    2 avg:   4.0 max:   28
# 23:36:15: 27/32: min:    2 avg:   4.0 max:   27
# 23:36:18: 28/32: min:    2 avg:   4.5 max:   29
# 23:36:21: 29/32: min:    2 avg:   4.2 max:   30
# 23:36:24: 30/32: min:    2 avg:   4.0 max:   27
# 23:36:27: 31/32: min:    2 avg:   4.5 max:   28
# 23:36:30: 32/32: min:    2 avg:   4.0 max:   26
# 23:36:30: Cyclictest completed. Actual execution time:0:01:39
# Terminated stress
# Min: 2 us
# Avg: 4.2 us
# Max: 32 us
# Max list: [25, 28, 29, 30, 32, 32]
# PASS

rt_bmark.intlat.vm [Min/us,Avg/us,Max/us]:
2,4.2,32
PASS: rt_bmark.intlat.vm

# ==============================================================================
#   Test case (6/6): rt_bmark.intlat.full
# ..............................................................................
# Starting stress(io+cpu+hdd+vm)
#   Command: 'stress -i 4 -c 4 -d 4 --hdd-bytes 20M -m 4 --vm-bytes 10M'
# Starting cyclictest
#   Command          : /opt/benchmarking/rt-tests/cyclictest -S -p 99 -q -i 100 -d 20 -l 30000
#   Number of cycles : 960000 (32 sets of 30000 cycles)
#   Exec. time (est) : 0:01:36
# 23:36:30: Start of execution
stress: info: [3175] dispatching hogs: 4 cpu, 4 io, 4 vm, 4 hdd
# 23:36:33:  1/32: min:    2 avg:   3.2 max:   51
# 23:36:36:  2/32: min:    2 avg:   3.2 max:   47
# 23:36:39:  3/32: min:    2 avg:   3.3 max:   43
# 23:36:43:  4/32: min:    2 avg:   3.2 max:   46
# 23:36:46:  5/32: min:    2 avg:   3.2 max:   60
# 23:36:49:  6/32: min:    2 avg:   3.2 max:   65
# 23:36:52:  7/32: min:    2 avg:   3.2 max:   24
# 23:36:55:  8/32: min:    2 avg:   3.5 max:   26
# 23:36:58:  9/32: min:    2 avg:   3.5 max:   76
# 23:37:01: 10/32: min:    2 avg:   3.5 max:   53
# 23:37:04: 11/32: min:    2 avg:   3.5 max:   62
# 23:37:08: 12/32: min:    2 avg:   3.5 max:   48
# 23:37:11: 13/32: min:    2 avg:   3.3 max:   59
# 23:37:14: 14/32: min:    2 avg:   3.3 max:   49
# 23:37:17: 15/32: min:    2 avg:   3.3 max:   60
# 23:37:20: 16/32: min:    2 avg:   3.3 max:   58
# 23:37:23: 17/32: min:    2 avg:   3.3 max:   55
# 23:37:26: 18/32: min:    2 avg:   3.3 max:   59
# 23:37:29: 19/32: min:    2 avg:   3.2 max:   66
# 23:37:33: 20/32: min:    2 avg:   3.2 max:   56
# 23:37:36: 21/32: min:    2 avg:   3.2 max:   82
# 23:37:39: 22/32: min:    2 avg:   3.2 max:   77
# 23:37:42: 23/32: min:    2 avg:   3.5 max:   41
# 23:37:45: 24/32: min:    2 avg:   3.3 max:   64
# 23:37:48: 25/32: min:    2 avg:   3.3 max:   28
# 23:37:51: 26/32: min:    2 avg:   3.3 max:   41
# 23:37:54: 27/32: min:    2 avg:   3.3 max:   46
# 23:37:58: 28/32: min:    2 avg:   3.5 max:   30
# 23:38:01: 29/32: min:    2 avg:   3.5 max:   87
# 23:38:04: 30/32: min:    2 avg:   3.3 max:   34
# 23:38:07: 31/32: min:    2 avg:   3.3 max:   71
# 23:38:10: 32/32: min:    2 avg:   3.0 max:   49
# 23:38:10: Cyclictest completed. Actual execution time:0:01:40
# Terminated stress
# Min: 2 us
# Avg: 3.3 us
# Max: 87 us
# Max list: [24, 26, 46, 65, 76, 87]
# PASS

rt_bmark.intlat.full [Min/us,Avg/us,Max/us]:
2,3.3,87
PASS: rt_bmark.intlat.full

MaxTang Core i7-8665U - RT Benchmark

Click to toggle results

# ==============================================================================
#   Test case (1/6): rt_bmark.intlat.no_stress
# ..............................................................................
# No stress requested
# Starting cyclictest
#   Command          : /opt/benchmarking/rt-tests/cyclictest -S -p 99 -q -i 100 -d 20 -l 30000
#   Number of cycles : 960000 (32 sets of 30000 cycles)
#   Exec. time (est) : 0:01:36
# Hung task detection not supported
#   (File /proc/sys/kernel/hung_task_timeout_secs not found)
# 20:30:31: Start of execution
# 20:30:34:  1/32: min:    1 avg:   2.0 max:    6
# 20:30:37:  2/32: min:    1 avg:   1.7 max:    8
# 20:30:40:  3/32: min:    1 avg:   2.0 max:    4
# 20:30:43:  4/32: min:    1 avg:   2.0 max:    5
# 20:30:46:  5/32: min:    1 avg:   2.0 max:    5
# 20:30:49:  6/32: min:    1 avg:   2.0 max:    5
# 20:30:52:  7/32: min:    1 avg:   2.0 max:    5
# 20:30:55:  8/32: min:    1 avg:   2.0 max:    4
# 20:30:59:  9/32: min:    1 avg:   2.0 max:    5
# 20:31:02: 10/32: min:    1 avg:   2.0 max:    5
# 20:31:05: 11/32: min:    1 avg:   2.0 max:    5
# 20:31:08: 12/32: min:    1 avg:   2.0 max:    5
# 20:31:11: 13/32: min:    1 avg:   2.0 max:    4
# 20:31:14: 14/32: min:    2 avg:   2.0 max:    5
# 20:31:17: 15/32: min:    1 avg:   2.0 max:    6
# 20:31:20: 16/32: min:    1 avg:   2.0 max:    4
# 20:31:23: 17/32: min:    2 avg:   2.0 max:    6
# 20:31:26: 18/32: min:    1 avg:   2.0 max:    6
# 20:31:29: 19/32: min:    1 avg:   2.0 max:    5
# 20:31:32: 20/32: min:    1 avg:   2.0 max:    6
# 20:31:35: 21/32: min:    1 avg:   2.0 max:    7
# 20:31:38: 22/32: min:    1 avg:   2.0 max:    4
# 20:31:41: 23/32: min:    1 avg:   2.0 max:    5
# 20:31:45: 24/32: min:    2 avg:   2.0 max:    5
# 20:31:48: 25/32: min:    1 avg:   2.0 max:    7
# 20:31:51: 26/32: min:    1 avg:   2.0 max:    5
# 20:31:54: 27/32: min:    1 avg:   2.0 max:    4
# 20:31:57: 28/32: min:    1 avg:   2.0 max:    4
# 20:32:00: 29/32: min:    1 avg:   2.0 max:    4
# 20:32:03: 30/32: min:    1 avg:   2.0 max:    5
# 20:32:06: 31/32: min:    1 avg:   2.0 max:    4
# 20:32:09: 32/32: min:    1 avg:   2.0 max:    6
# 20:32:09: Cyclictest completed. Actual execution time:0:01:38
# Min: 1 us
# Avg: 2.0 us
# Max: 8 us
# Max list: [4, 4, 5, 6, 7, 8]
# PASS

rt_bmark.intlat.no_stress [Min/us,Avg/us,Max/us]:
1,2.0,8
PASS: rt_bmark.intlat.no_stress

# ==============================================================================
#   Test case (2/6): rt_bmark.intlat.cpu
# ..............................................................................
# Starting stress(cpu)
#   Command: 'stress -c 4'
# Starting cyclictest
#   Command          : /opt/benchmarking/rt-tests/cyclictest -S -p 99 -q -i 100 -d 20 -l 30000
#   Number of cycles : 960000 (32 sets of 30000 cycles)
#   Exec. time (est) : 0:01:36
# 20:32:09: Start of execution
stress: info: [2505] dispatching hogs: 4 cpu, 0 io, 0 vm, 0 hdd
# 20:32:12:  1/32: min:    1 avg:   2.0 max:    5
# 20:32:15:  2/32: min:    2 avg:   2.0 max:    4
# 20:32:18:  3/32: min:    2 avg:   2.0 max:    4
# 20:32:21:  4/32: min:    2 avg:   2.0 max:    6
# 20:32:25:  5/32: min:    2 avg:   2.0 max:    4
# 20:32:28:  6/32: min:    2 avg:   2.0 max:    6
# 20:32:31:  7/32: min:    2 avg:   2.0 max:    5
# 20:32:34:  8/32: min:    2 avg:   2.0 max:    7
# 20:32:37:  9/32: min:    2 avg:   2.0 max:    5
# 20:32:40: 10/32: min:    2 avg:   2.0 max:    8
# 20:32:43: 11/32: min:    2 avg:   2.0 max:    4
# 20:32:46: 12/32: min:    2 avg:   2.0 max:    8
# 20:32:50: 13/32: min:    2 avg:   2.0 max:    4
# 20:32:53: 14/32: min:    2 avg:   2.0 max:    4
# 20:32:56: 15/32: min:    2 avg:   2.0 max:    4
# 20:32:59: 16/32: min:    2 avg:   2.0 max:    5
# 20:33:02: 17/32: min:    2 avg:   2.0 max:    6
# 20:33:05: 18/32: min:    2 avg:   2.0 max:    6
# 20:33:08: 19/32: min:    2 avg:   2.0 max:    5
# 20:33:11: 20/32: min:    2 avg:   2.0 max:    5
# 20:33:14: 21/32: min:    2 avg:   2.0 max:    7
# 20:33:18: 22/32: min:    2 avg:   2.0 max:    4
# 20:33:21: 23/32: min:    2 avg:   2.0 max:    7
# 20:33:24: 24/32: min:    2 avg:   2.0 max:    7
# 20:33:27: 25/32: min:    2 avg:   2.0 max:    4
# 20:33:30: 26/32: min:    2 avg:   2.0 max:    5
# 20:33:33: 27/32: min:    2 avg:   2.0 max:    5
# 20:33:36: 28/32: min:    2 avg:   2.0 max:    5
# 20:33:39: 29/32: min:    2 avg:   2.0 max:    7
# 20:33:43: 30/32: min:    2 avg:   2.0 max:    6
# 20:33:46: 31/32: min:    2 avg:   2.0 max:    7
# 20:33:49: 32/32: min:    2 avg:   2.0 max:    7
# 20:33:49: Cyclictest completed. Actual execution time:0:01:40
# Terminated stress
# Min: 1 us
# Avg: 2.0 us
# Max: 8 us
# Max list: [4, 4, 5, 7, 7, 8]
# PASS

rt_bmark.intlat.cpu [Min/us,Avg/us,Max/us]:
1,2.0,8
PASS: rt_bmark.intlat.cpu

# ==============================================================================
#   Test case (3/6): rt_bmark.intlat.hdd
# ..............................................................................
# Starting stress(hdd)
#   Command: 'stress -d 4 --hdd-bytes 20M'
# Starting cyclictest
#   Command          : /opt/benchmarking/rt-tests/cyclictest -S -p 99 -q -i 100 -d 20 -l 30000
#   Number of cycles : 960000 (32 sets of 30000 cycles)
#   Exec. time (est) : 0:01:36
# 20:33:49: Start of execution
stress: info: [2670] dispatching hogs: 0 cpu, 0 io, 0 vm, 4 hdd
# 20:33:52:  1/32: min:    2 avg:   2.5 max:   12
# 20:33:55:  2/32: min:    2 avg:   2.5 max:   10
# 20:33:58:  3/32: min:    2 avg:   2.5 max:   14
# 20:34:01:  4/32: min:    2 avg:   2.5 max:   11
# 20:34:04:  5/32: min:    2 avg:   2.5 max:    9
# 20:34:07:  6/32: min:    2 avg:   2.5 max:   10
# 20:34:11:  7/32: min:    2 avg:   2.5 max:   12
# 20:34:14:  8/32: min:    2 avg:   2.5 max:   10
# 20:34:17:  9/32: min:    2 avg:   2.5 max:   10
# 20:34:20: 10/32: min:    2 avg:   2.5 max:    9
# 20:34:23: 11/32: min:    2 avg:   2.5 max:    9
# 20:34:26: 12/32: min:    2 avg:   2.5 max:   11
# 20:34:29: 13/32: min:    2 avg:   2.5 max:    8
# 20:34:32: 14/32: min:    2 avg:   2.5 max:   11
# 20:34:35: 15/32: min:    2 avg:   2.5 max:   13
# 20:34:39: 16/32: min:    2 avg:   2.5 max:   11
# 20:34:42: 17/32: min:    2 avg:   2.5 max:   10
# 20:34:45: 18/32: min:    2 avg:   2.5 max:   12
# 20:34:48: 19/32: min:    2 avg:   2.5 max:    9
# 20:34:51: 20/32: min:    2 avg:   2.5 max:   10
# 20:34:54: 21/32: min:    2 avg:   2.5 max:   12
# 20:34:57: 22/32: min:    2 avg:   2.5 max:   10
# 20:35:00: 23/32: min:    2 avg:   2.5 max:   11
# 20:35:03: 24/32: min:    2 avg:   2.5 max:   10
# 20:35:07: 25/32: min:    2 avg:   2.5 max:   10
# 20:35:10: 26/32: min:    2 avg:   2.5 max:   10
# 20:35:13: 27/32: min:    2 avg:   2.5 max:   11
# 20:35:16: 28/32: min:    2 avg:   2.5 max:   11
# 20:35:19: 29/32: min:    2 avg:   2.5 max:    9
# 20:35:22: 30/32: min:    2 avg:   2.5 max:   12
# 20:35:25: 31/32: min:    2 avg:   2.5 max:    9
# 20:35:28: 32/32: min:    2 avg:   2.5 max:   11
# 20:35:28: Cyclictest completed. Actual execution time:0:01:40
# Terminated stress
# Min: 2 us
# Avg: 2.5 us
# Max: 14 us
# Max list: [8, 10, 11, 12, 12, 14]
# PASS

rt_bmark.intlat.hdd [Min/us,Avg/us,Max/us]:
2,2.5,14
PASS: rt_bmark.intlat.hdd

# ==============================================================================
#   Test case (4/6): rt_bmark.intlat.io
# ..............................................................................
# Starting stress(io)
#   Command: 'stress -i 4'
# Starting cyclictest
#   Command          : /opt/benchmarking/rt-tests/cyclictest -S -p 99 -q -i 100 -d 20 -l 30000
#   Number of cycles : 960000 (32 sets of 30000 cycles)
#   Exec. time (est) : 0:01:36
# 20:35:28: Start of execution
stress: info: [2836] dispatching hogs: 0 cpu, 4 io, 0 vm, 0 hdd
# 20:35:31:  1/32: min:    1 avg:   2.0 max:    8
# 20:35:34:  2/32: min:    1 avg:   2.0 max:    8
# 20:35:38:  3/32: min:    1 avg:   2.0 max:    6
# 20:35:41:  4/32: min:    1 avg:   2.0 max:    6
# 20:35:44:  5/32: min:    1 avg:   2.0 max:    7
# 20:35:47:  6/32: min:    1 avg:   2.0 max:    5
# 20:35:50:  7/32: min:    1 avg:   2.0 max:    6
# 20:35:53:  8/32: min:    1 avg:   2.0 max:    6
# 20:35:56:  9/32: min:    1 avg:   2.0 max:    6
# 20:35:59: 10/32: min:    1 avg:   2.0 max:    8
# 20:36:02: 11/32: min:    2 avg:   2.0 max:    6
# 20:36:05: 12/32: min:    1 avg:   2.0 max:    6
# 20:36:08: 13/32: min:    1 avg:   2.0 max:    6
# 20:36:11: 14/32: min:    1 avg:   2.0 max:    7
# 20:36:14: 15/32: min:    1 avg:   2.0 max:    5
# 20:36:17: 16/32: min:    1 avg:   2.0 max:    6
# 20:36:21: 17/32: min:    1 avg:   2.0 max:    6
# 20:36:24: 18/32: min:    1 avg:   2.0 max:    7
# 20:36:27: 19/32: min:    1 avg:   2.0 max:    7
# 20:36:30: 20/32: min:    1 avg:   2.0 max:    6
# 20:36:33: 21/32: min:    1 avg:   2.0 max:    6
# 20:36:36: 22/32: min:    1 avg:   2.0 max:    7
# 20:36:39: 23/32: min:    1 avg:   2.0 max:    7
# 20:36:42: 24/32: min:    1 avg:   2.0 max:    6
# 20:36:45: 25/32: min:    2 avg:   2.0 max:    6
# 20:36:48: 26/32: min:    1 avg:   2.0 max:    5
# 20:36:51: 27/32: min:    1 avg:   2.0 max:    6
# 20:36:54: 28/32: min:    1 avg:   2.0 max:    6
# 20:36:57: 29/32: min:    1 avg:   2.0 max:    7
# 20:37:00: 30/32: min:    1 avg:   2.0 max:    6
# 20:37:03: 31/32: min:    1 avg:   2.0 max:    5
# 20:37:07: 32/32: min:    1 avg:   2.0 max:    7
# 20:37:07: Cyclictest completed. Actual execution time:0:01:38
# Terminated stress
# Min: 1 us
# Avg: 2.0 us
# Max: 8 us
# Max list: [5, 6, 6, 7, 7, 8]
# PASS

rt_bmark.intlat.io [Min/us,Avg/us,Max/us]:
1,2.0,8
PASS: rt_bmark.intlat.io

# ==============================================================================
#   Test case (5/6): rt_bmark.intlat.vm
# ..............................................................................
# Starting stress(vm)
#   Command: 'stress -m 4 --vm-bytes 10M'
# Starting cyclictest
#   Command          : /opt/benchmarking/rt-tests/cyclictest -S -p 99 -q -i 100 -d 20 -l 30000
#   Number of cycles : 960000 (32 sets of 30000 cycles)
#   Exec. time (est) : 0:01:36
# 20:37:07: Start of execution
stress: info: [3001] dispatching hogs: 0 cpu, 0 io, 4 vm, 0 hdd
# 20:37:10:  1/32: min:    2 avg:   3.0 max:   19
# 20:37:13:  2/32: min:    2 avg:   3.0 max:   16
# 20:37:16:  3/32: min:    2 avg:   3.3 max:   20
# 20:37:19:  4/32: min:    2 avg:   3.0 max:   21
# 20:37:22:  5/32: min:    2 avg:   3.0 max:   18
# 20:37:25:  6/32: min:    2 avg:   3.0 max:   18
# 20:37:28:  7/32: min:    2 avg:   3.0 max:   21
# 20:37:31:  8/32: min:    2 avg:   3.0 max:   20
# 20:37:35:  9/32: min:    2 avg:   3.0 max:   19
# 20:37:38: 10/32: min:    2 avg:   3.5 max:   21
# 20:37:41: 11/32: min:    2 avg:   3.0 max:   20
# 20:37:44: 12/32: min:    2 avg:   3.0 max:   18
# 20:37:47: 13/32: min:    2 avg:   3.0 max:   20
# 20:37:50: 14/32: min:    2 avg:   3.0 max:   20
# 20:37:53: 15/32: min:    2 avg:   3.0 max:   21
# 20:37:56: 16/32: min:    2 avg:   3.0 max:   14
# 20:37:59: 17/32: min:    2 avg:   3.0 max:   24
# 20:38:03: 18/32: min:    2 avg:   3.0 max:   20
# 20:38:06: 19/32: min:    2 avg:   3.0 max:   21
# 20:38:09: 20/32: min:    2 avg:   3.0 max:   15
# 20:38:12: 21/32: min:    2 avg:   3.0 max:   22
# 20:38:15: 22/32: min:    2 avg:   3.0 max:   18
# 20:38:18: 23/32: min:    2 avg:   3.0 max:   19
# 20:38:21: 24/32: min:    2 avg:   3.0 max:   19
# 20:38:24: 25/32: min:    2 avg:   3.0 max:   18
# 20:38:27: 26/32: min:    2 avg:   3.0 max:   17
# 20:38:30: 27/32: min:    2 avg:   3.0 max:   19
# 20:38:34: 28/32: min:    2 avg:   3.0 max:   20
# 20:38:37: 29/32: min:    2 avg:   3.0 max:   20
# 20:38:40: 30/32: min:    2 avg:   3.0 max:   22
# 20:38:43: 31/32: min:    2 avg:   3.0 max:   19
# 20:38:46: 32/32: min:    2 avg:   3.0 max:   23
# 20:38:46: Cyclictest completed. Actual execution time:0:01:39
# Terminated stress
# Min: 2 us
# Avg: 3.0 us
# Max: 24 us
# Max list: [14, 18, 20, 21, 21, 24]
# PASS

rt_bmark.intlat.vm [Min/us,Avg/us,Max/us]:
2,3.0,24
PASS: rt_bmark.intlat.vm

# ==============================================================================
#   Test case (6/6): rt_bmark.intlat.full
# ..............................................................................
# Starting stress(io+cpu+hdd+vm)
#   Command: 'stress -i 4 -c 4 -d 4 --hdd-bytes 20M -m 4 --vm-bytes 10M'
# Starting cyclictest
#   Command          : /opt/benchmarking/rt-tests/cyclictest -S -p 99 -q -i 100 -d 20 -l 30000
#   Number of cycles : 960000 (32 sets of 30000 cycles)
#   Exec. time (est) : 0:01:36
# 20:38:46: Start of execution
stress: info: [3166] dispatching hogs: 4 cpu, 4 io, 4 vm, 4 hdd
# 20:38:49:  1/32: min:    2 avg:   2.5 max:   17
# 20:38:52:  2/32: min:    2 avg:   2.5 max:   20
# 20:38:55:  3/32: min:    2 avg:   2.5 max:   16
# 20:38:58:  4/32: min:    2 avg:   2.5 max:   17
# 20:39:02:  5/32: min:    2 avg:   2.2 max:   20
# 20:39:05:  6/32: min:    2 avg:   2.7 max:   15
# 20:39:08:  7/32: min:    2 avg:   2.5 max:   17
# 20:39:11:  8/32: min:    2 avg:   2.5 max:   17
# 20:39:14:  9/32: min:    1 avg:   2.5 max:   18
# 20:39:17: 10/32: min:    2 avg:   2.5 max:   15
# 20:39:20: 11/32: min:    2 avg:   2.5 max:   20
# 20:39:23: 12/32: min:    2 avg:   2.5 max:   17
# 20:39:26: 13/32: min:    2 avg:   2.5 max:   19
# 20:39:30: 14/32: min:    2 avg:   2.5 max:   19
# 20:39:33: 15/32: min:    2 avg:   2.5 max:   16
# 20:39:36: 16/32: min:    2 avg:   2.5 max:   17
# 20:39:39: 17/32: min:    2 avg:   2.5 max:   21
# 20:39:42: 18/32: min:    2 avg:   2.7 max:   14
# 20:39:45: 19/32: min:    2 avg:   2.5 max:   18
# 20:39:48: 20/32: min:    2 avg:   2.5 max:   24
# 20:39:52: 21/32: min:    2 avg:   2.5 max:   15
# 20:39:55: 22/32: min:    2 avg:   2.5 max:   17
# 20:39:58: 23/32: min:    2 avg:   2.5 max:   15
# 20:40:01: 24/32: min:    2 avg:   2.5 max:   17
# 20:40:04: 25/32: min:    2 avg:   2.2 max:   16
# 20:40:07: 26/32: min:    2 avg:   2.5 max:   21
# 20:40:10: 27/32: min:    1 avg:   2.5 max:   14
# 20:40:13: 28/32: min:    2 avg:   2.3 max:   13
# 20:40:16: 29/32: min:    2 avg:   2.5 max:   16
# 20:40:20: 30/32: min:    2 avg:   2.5 max:   18
# 20:40:23: 31/32: min:    2 avg:   2.5 max:   15
# 20:40:26: 32/32: min:    2 avg:   2.5 max:   18
# 20:40:26: Cyclictest completed. Actual execution time:0:01:40
# Terminated stress
# Min: 1 us
# Avg: 2.5 us
# Max: 24 us
# Max list: [13, 14, 17, 20, 20, 24]
# PASS

rt_bmark.intlat.full [Min/us,Avg/us,Max/us]:
1,2.5,24
PASS: rt_bmark.intlat.full

Vecow Core i7-1185G7E - RT Benchmark

Click to toggle the results

# ==============================================================================
#   Test case (1/6): rt_bmark.intlat.no_stress
# ..............................................................................
# No stress requested
# Starting cyclictest
#   Command          : /opt/benchmarking/rt-tests/cyclictest -S -p 99 -q -i 100 -d 20 -l 30000
#   Number of cycles : 960000 (32 sets of 30000 cycles)
#   Exec. time (est) : 0:01:36
# Hung task detection not supported
#   (File /proc/sys/kernel/hung_task_timeout_secs not found)
# 16:23:11: Start of execution
# 16:23:14:  1/32: min:    1 avg:   1.0 max:    6
# 16:23:17:  2/32: min:    1 avg:   1.0 max:    6
# 16:23:20:  3/32: min:    1 avg:   1.0 max:    6
# 16:23:23:  4/32: min:    1 avg:   1.0 max:    6
# 16:23:26:  5/32: min:    1 avg:   1.0 max:    4
# 16:23:29:  6/32: min:    1 avg:   1.0 max:    4
# 16:23:33:  7/32: min:    1 avg:   1.0 max:    5
# 16:23:36:  8/32: min:    1 avg:   1.0 max:    4
# 16:23:39:  9/32: min:    1 avg:   1.0 max:    4
# 16:23:42: 10/32: min:    1 avg:   1.0 max:    4
# 16:23:45: 11/32: min:    1 avg:   1.0 max:    6
# 16:23:48: 12/32: min:    1 avg:   1.0 max:    6
# 16:23:51: 13/32: min:    1 avg:   1.0 max:    6
# 16:23:54: 14/32: min:    1 avg:   1.0 max:    5
# 16:23:57: 15/32: min:    1 avg:   1.0 max:    5
# 16:24:00: 16/32: min:    1 avg:   1.0 max:    4
# 16:24:03: 17/32: min:    1 avg:   1.0 max:    5
# 16:24:06: 18/32: min:    1 avg:   1.0 max:    5
# 16:24:09: 19/32: min:    1 avg:   1.0 max:    6
# 16:24:12: 20/32: min:    1 avg:   1.0 max:    5
# 16:24:15: 21/32: min:    1 avg:   1.0 max:    5
# 16:24:19: 22/32: min:    1 avg:   1.0 max:    6
# 16:24:22: 23/32: min:    1 avg:   1.0 max:    5
# 16:24:25: 24/32: min:    1 avg:   1.0 max:    5
# 16:24:28: 25/32: min:    1 avg:   1.0 max:    4
# 16:24:31: 26/32: min:    1 avg:   1.0 max:    5
# 16:24:34: 27/32: min:    1 avg:   1.0 max:    4
# 16:24:37: 28/32: min:    1 avg:   1.0 max:    6
# 16:24:40: 29/32: min:    1 avg:   1.0 max:    4
# 16:24:43: 30/32: min:    1 avg:   1.0 max:    4
# 16:24:46: 31/32: min:    1 avg:   1.0 max:    5
# 16:24:49: 32/32: min:    1 avg:   1.0 max:    4
# 16:24:49: Cyclictest completed. Actual execution time:0:01:38
# Min: 1 us
# Avg: 1.0 us
# Max: 6 us
# Max list: [4, 4, 5, 6, 6, 6]
# PASS

rt_bmark.intlat.no_stress [Min/us,Avg/us,Max/us]:
1,1.0,6
PASS: rt_bmark.intlat.no_stress

# ==============================================================================
#   Test case (2/6): rt_bmark.intlat.cpu
# ..............................................................................
# Starting stress(cpu)
#   Command: 'stress -c 4'
# Starting cyclictest
#   Command          : /opt/benchmarking/rt-tests/cyclictest -S -p 99 -q -i 100 -d 20 -l 30000
#   Number of cycles : 960000 (32 sets of 30000 cycles)
#   Exec. time (est) : 0:01:36
# 16:24:49: Start of execution
stress: info: [2323] dispatching hogs: 4 cpu, 0 io, 0 vm, 0 hdd
# 16:24:52:  1/32: min:    1 avg:   1.0 max:    6
# 16:24:55:  2/32: min:    1 avg:   1.0 max:    4
# 16:24:59:  3/32: min:    1 avg:   1.0 max:    4
# 16:25:02:  4/32: min:    1 avg:   1.0 max:    5
# 16:25:05:  5/32: min:    1 avg:   1.0 max:    4
# 16:25:08:  6/32: min:    1 avg:   1.0 max:    4
# 16:25:11:  7/32: min:    1 avg:   1.0 max:    4
# 16:25:14:  8/32: min:    1 avg:   1.0 max:    4
# 16:25:17:  9/32: min:    1 avg:   1.0 max:    4
# 16:25:20: 10/32: min:    1 avg:   1.0 max:    4
# 16:25:23: 11/32: min:    1 avg:   1.0 max:    4
# 16:25:26: 12/32: min:    1 avg:   1.0 max:    7
# 16:25:30: 13/32: min:    1 avg:   1.0 max:    5
# 16:25:33: 14/32: min:    1 avg:   1.0 max:    5
# 16:25:36: 15/32: min:    1 avg:   1.0 max:    5
# 16:25:39: 16/32: min:    1 avg:   1.0 max:    5
# 16:25:42: 17/32: min:    1 avg:   1.0 max:    5
# 16:25:45: 18/32: min:    1 avg:   1.0 max:    5
# 16:25:48: 19/32: min:    1 avg:   1.0 max:    4
# 16:25:51: 20/32: min:    1 avg:   1.0 max:    6
# 16:25:55: 21/32: min:    1 avg:   1.0 max:    4
# 16:25:58: 22/32: min:    1 avg:   1.0 max:    6
# 16:26:01: 23/32: min:    1 avg:   1.0 max:    5
# 16:26:04: 24/32: min:    1 avg:   1.0 max:    6
# 16:26:07: 25/32: min:    1 avg:   1.0 max:    6
# 16:26:10: 26/32: min:    1 avg:   1.0 max:    6
# 16:26:13: 27/32: min:    1 avg:   1.0 max:    4
# 16:26:16: 28/32: min:    1 avg:   1.0 max:    4
# 16:26:19: 29/32: min:    1 avg:   1.0 max:    4
# 16:26:23: 30/32: min:    1 avg:   1.0 max:    7
# 16:26:26: 31/32: min:    1 avg:   1.0 max:    5
# 16:26:29: 32/32: min:    1 avg:   1.0 max:    6
# 16:26:29: Cyclictest completed. Actual execution time:0:01:39
# Terminated stress
# Min: 1 us
# Avg: 1.0 us
# Max: 7 us
# Max list: [4, 4, 4, 6, 7, 7]
# PASS

rt_bmark.intlat.cpu [Min/us,Avg/us,Max/us]:
1,1.0,7
PASS: rt_bmark.intlat.cpu

# ==============================================================================
#   Test case (3/6): rt_bmark.intlat.hdd
# ..............................................................................
# Starting stress(hdd)
#   Command: 'stress -d 4 --hdd-bytes 20M'
# Starting cyclictest
#   Command          : /opt/benchmarking/rt-tests/cyclictest -S -p 99 -q -i 100 -d 20 -l 30000
#   Number of cycles : 960000 (32 sets of 30000 cycles)
#   Exec. time (est) : 0:01:36
# 16:26:29: Start of execution
stress: info: [2488] dispatching hogs: 0 cpu, 0 io, 0 vm, 4 hdd
# 16:26:32:  1/32: min:    1 avg:   1.7 max:    9
# 16:26:35:  2/32: min:    1 avg:   2.0 max:   10
# 16:26:38:  3/32: min:    1 avg:   2.0 max:   10
# 16:26:41:  4/32: min:    1 avg:   2.0 max:   10
# 16:26:44:  5/32: min:    1 avg:   2.0 max:   11
# 16:26:47:  6/32: min:    1 avg:   2.0 max:   10
# 16:26:50:  7/32: min:    1 avg:   2.0 max:    8
# 16:26:54:  8/32: min:    1 avg:   2.0 max:   10
# 16:26:57:  9/32: min:    1 avg:   2.0 max:   10
# 16:27:00: 10/32: min:    1 avg:   2.0 max:    8
# 16:27:03: 11/32: min:    1 avg:   2.0 max:   10
# 16:27:06: 12/32: min:    1 avg:   2.0 max:   11
# 16:27:09: 13/32: min:    1 avg:   2.0 max:   12
# 16:27:12: 14/32: min:    1 avg:   2.0 max:    9
# 16:27:15: 15/32: min:    1 avg:   2.0 max:   10
# 16:27:18: 16/32: min:    1 avg:   2.0 max:   10
# 16:27:22: 17/32: min:    1 avg:   2.0 max:    8
# 16:27:25: 18/32: min:    1 avg:   2.0 max:   10
# 16:27:28: 19/32: min:    1 avg:   2.0 max:   10
# 16:27:31: 20/32: min:    1 avg:   2.0 max:   10
# 16:27:34: 21/32: min:    1 avg:   2.0 max:   11
# 16:27:37: 22/32: min:    1 avg:   2.0 max:   10
# 16:27:40: 23/32: min:    1 avg:   2.0 max:   10
# 16:27:43: 24/32: min:    1 avg:   2.0 max:   11
# 16:27:47: 25/32: min:    1 avg:   2.0 max:    9
# 16:27:50: 26/32: min:    1 avg:   2.0 max:    9
# 16:27:53: 27/32: min:    1 avg:   2.0 max:   10
# 16:27:56: 28/32: min:    1 avg:   2.0 max:   11
# 16:27:59: 29/32: min:    1 avg:   2.0 max:   10
# 16:28:02: 30/32: min:    1 avg:   2.0 max:    9
# 16:28:05: 31/32: min:    1 avg:   2.0 max:   11
# 16:28:08: 32/32: min:    1 avg:   2.0 max:   10
# 16:28:08: Cyclictest completed. Actual execution time:0:01:40
# Terminated stress
# Min: 1 us
# Avg: 2.0 us
# Max: 12 us
# Max list: [8, 9, 10, 11, 11, 12]
# PASS

rt_bmark.intlat.hdd [Min/us,Avg/us,Max/us]:
1,2.0,12
PASS: rt_bmark.intlat.hdd

# ==============================================================================
#   Test case (4/6): rt_bmark.intlat.io
# ..............................................................................
# Starting stress(io)
#   Command: 'stress -i 4'
# Starting cyclictest
#   Command          : /opt/benchmarking/rt-tests/cyclictest -S -p 99 -q -i 100 -d 20 -l 30000
#   Number of cycles : 960000 (32 sets of 30000 cycles)
#   Exec. time (est) : 0:01:36
# 16:28:08: Start of execution
stress: info: [2659] dispatching hogs: 0 cpu, 4 io, 0 vm, 0 hdd
# 16:28:11:  1/32: min:    1 avg:   1.0 max:    6
# 16:28:14:  2/32: min:    1 avg:   1.0 max:    5
# 16:28:17:  3/32: min:    1 avg:   1.0 max:    5
# 16:28:21:  4/32: min:    1 avg:   1.0 max:    5
# 16:28:24:  5/32: min:    1 avg:   1.0 max:    5
# 16:28:27:  6/32: min:    1 avg:   1.0 max:    6
# 16:28:30:  7/32: min:    1 avg:   1.0 max:    6
# 16:28:33:  8/32: min:    1 avg:   1.0 max:    5
# 16:28:36:  9/32: min:    1 avg:   1.0 max:    6
# 16:28:39: 10/32: min:    1 avg:   1.0 max:    5
# 16:28:42: 11/32: min:    1 avg:   1.0 max:    5
# 16:28:45: 12/32: min:    1 avg:   1.0 max:    5
# 16:28:48: 13/32: min:    1 avg:   1.0 max:    5
# 16:28:51: 14/32: min:    1 avg:   1.0 max:    4
# 16:28:54: 15/32: min:    1 avg:   1.0 max:    5
# 16:28:57: 16/32: min:    1 avg:   1.0 max:   11
# 16:29:00: 17/32: min:    1 avg:   1.0 max:    7
# 16:29:04: 18/32: min:    1 avg:   1.0 max:    5
# 16:29:07: 19/32: min:    1 avg:   1.0 max:    5
# 16:29:10: 20/32: min:    1 avg:   1.0 max:    5
# 16:29:13: 21/32: min:    1 avg:   1.0 max:    6
# 16:29:16: 22/32: min:    1 avg:   1.0 max:   11
# 16:29:19: 23/32: min:    1 avg:   1.0 max:    8
# 16:29:22: 24/32: min:    1 avg:   1.0 max:    5
# 16:29:25: 25/32: min:    1 avg:   1.0 max:    9
# 16:29:28: 26/32: min:    1 avg:   1.0 max:    7
# 16:29:31: 27/32: min:    1 avg:   1.0 max:    7
# 16:29:34: 28/32: min:    1 avg:   1.0 max:    6
# 16:29:37: 29/32: min:    1 avg:   1.0 max:   10
# 16:29:40: 30/32: min:    1 avg:   1.0 max:    5
# 16:29:43: 31/32: min:    1 avg:   1.0 max:    6
# 16:29:46: 32/32: min:    1 avg:   1.0 max:    5
# 16:29:46: Cyclictest completed. Actual execution time:0:01:38
# Terminated stress
# Min: 1 us
# Avg: 1.0 us
# Max: 11 us
# Max list: [4, 5, 6, 6, 11, 11]
# PASS

rt_bmark.intlat.io [Min/us,Avg/us,Max/us]:
1,1.0,11
PASS: rt_bmark.intlat.io

# ==============================================================================
#   Test case (5/6): rt_bmark.intlat.vm
# ..............................................................................
# Starting stress(vm)
#   Command: 'stress -m 4 --vm-bytes 10M'
# Starting cyclictest
#   Command          : /opt/benchmarking/rt-tests/cyclictest -S -p 99 -q -i 100 -d 20 -l 30000
#   Number of cycles : 960000 (32 sets of 30000 cycles)
#   Exec. time (est) : 0:01:36
# 16:29:46: Start of execution
stress: info: [2825] dispatching hogs: 0 cpu, 0 io, 4 vm, 0 hdd
# 16:29:50:  1/32: min:    1 avg:   3.0 max:   12
# 16:29:53:  2/32: min:    1 avg:   3.0 max:   11
# 16:29:56:  3/32: min:    1 avg:   3.0 max:   10
# 16:29:59:  4/32: min:    1 avg:   3.0 max:   11
# 16:30:02:  5/32: min:    1 avg:   3.0 max:   10
# 16:30:05:  6/32: min:    1 avg:   3.0 max:   10
# 16:30:08:  7/32: min:    1 avg:   3.0 max:   11
# 16:30:11:  8/32: min:    1 avg:   3.0 max:   12
# 16:30:14:  9/32: min:    1 avg:   3.0 max:   10
# 16:30:18: 10/32: min:    1 avg:   3.0 max:   10
# 16:30:21: 11/32: min:    1 avg:   3.0 max:   10
# 16:30:24: 12/32: min:    1 avg:   3.0 max:   11
# 16:30:27: 13/32: min:    1 avg:   3.0 max:   10
# 16:30:30: 14/32: min:    1 avg:   3.0 max:    9
# 16:30:33: 15/32: min:    1 avg:   3.0 max:    9
# 16:30:36: 16/32: min:    1 avg:   3.0 max:    9
# 16:30:39: 17/32: min:    1 avg:   3.0 max:   11
# 16:30:42: 18/32: min:    1 avg:   3.0 max:   10
# 16:30:45: 19/32: min:    1 avg:   3.0 max:   11
# 16:30:49: 20/32: min:    1 avg:   3.0 max:   10
# 16:30:52: 21/32: min:    1 avg:   3.2 max:   12
# 16:30:55: 22/32: min:    1 avg:   3.2 max:   10
# 16:30:58: 23/32: min:    1 avg:   3.5 max:    9
# 16:31:01: 24/32: min:    1 avg:   3.0 max:   10
# 16:31:04: 25/32: min:    1 avg:   3.0 max:    9
# 16:31:07: 26/32: min:    1 avg:   3.3 max:    9
# 16:31:10: 27/32: min:    1 avg:   3.3 max:   10
# 16:31:13: 28/32: min:    1 avg:   3.2 max:   10
# 16:31:17: 29/32: min:    1 avg:   3.2 max:    9
# 16:31:20: 30/32: min:    1 avg:   3.0 max:    9
# 16:31:23: 31/32: min:    1 avg:   3.0 max:   10
# 16:31:26: 32/32: min:    1 avg:   3.2 max:    8
# 16:31:26: Cyclictest completed. Actual execution time:0:01:39
# Terminated stress
# Min: 1 us
# Avg: 3.1 us
# Max: 12 us
# Max list: [8, 9, 10, 10, 12, 12]
# PASS

rt_bmark.intlat.vm [Min/us,Avg/us,Max/us]:
1,3.1,12
PASS: rt_bmark.intlat.vm

# ==============================================================================
#   Test case (6/6): rt_bmark.intlat.full
# ..............................................................................
# Starting stress(io+cpu+hdd+vm)
#   Command: 'stress -i 4 -c 4 -d 4 --hdd-bytes 20M -m 4 --vm-bytes 10M'
# Starting cyclictest
#   Command          : /opt/benchmarking/rt-tests/cyclictest -S -p 99 -q -i 100 -d 20 -l 30000
#   Number of cycles : 960000 (32 sets of 30000 cycles)
#   Exec. time (est) : 0:01:36
# 16:31:26: Start of execution
stress: info: [2990] dispatching hogs: 4 cpu, 4 io, 4 vm, 4 hdd
# 16:31:29:  1/32: min:    1 avg:   2.0 max:   11
# 16:31:32:  2/32: min:    1 avg:   2.0 max:   11
# 16:31:35:  3/32: min:    1 avg:   2.0 max:   11
# 16:31:38:  4/32: min:    1 avg:   2.0 max:   12
# 16:31:41:  5/32: min:    1 avg:   2.0 max:   13
# 16:31:45:  6/32: min:    1 avg:   2.0 max:   13
# 16:31:48:  7/32: min:    1 avg:   2.0 max:   13
# 16:31:51:  8/32: min:    1 avg:   2.0 max:   12
# 16:31:54:  9/32: min:    1 avg:   2.0 max:   11
# 16:31:57: 10/32: min:    1 avg:   2.0 max:   12
# 16:32:00: 11/32: min:    1 avg:   2.0 max:   10
# 16:32:03: 12/32: min:    1 avg:   2.3 max:   12
# 16:32:06: 13/32: min:    1 avg:   2.0 max:   13
# 16:32:10: 14/32: min:    1 avg:   2.0 max:   11
# 16:32:13: 15/32: min:    1 avg:   2.0 max:   12
# 16:32:16: 16/32: min:    1 avg:   2.0 max:   11
# 16:32:19: 17/32: min:    1 avg:   2.0 max:   13
# 16:32:22: 18/32: min:    1 avg:   2.0 max:   11
# 16:32:25: 19/32: min:    1 avg:   2.0 max:   11
# 16:32:28: 20/32: min:    1 avg:   2.0 max:   12
# 16:32:31: 21/32: min:    1 avg:   2.0 max:   11
# 16:32:34: 22/32: min:    1 avg:   2.0 max:   11
# 16:32:38: 23/32: min:    1 avg:   2.0 max:   12
# 16:32:41: 24/32: min:    1 avg:   2.0 max:   13
# 16:32:44: 25/32: min:    1 avg:   2.0 max:   11
# 16:32:47: 26/32: min:    1 avg:   2.0 max:   11
# 16:32:50: 27/32: min:    1 avg:   2.0 max:   12
# 16:32:53: 28/32: min:    1 avg:   2.0 max:   13
# 16:32:56: 29/32: min:    1 avg:   2.0 max:   11
# 16:32:59: 30/32: min:    1 avg:   2.0 max:   10
# 16:33:02: 31/32: min:    1 avg:   2.0 max:   12
# 16:33:06: 32/32: min:    1 avg:   2.0 max:   13
# 16:33:06: Cyclictest completed. Actual execution time:0:01:40
# Terminated stress
# Min: 1 us
# Avg: 2.0 us
# Max: 13 us
# Max list: [10, 11, 12, 13, 13, 13]
# PASS

rt_bmark.intlat.full [Min/us,Avg/us,Max/us]:
1,2.0,13
PASS: rt_bmark.intlat.full

Karbon 700 Core i7-9700TE - RT Benchmark

Click to toggle the results

# ==============================================================================
#   Test case (1/6): rt_bmark.intlat.no_stress
# ..............................................................................
# No stress requested
# Starting cyclictest
#   Command          : /opt/benchmarking/rt-tests/cyclictest -S -p 99 -q -i 100 -d 20 -l 30000
#   Number of cycles : 960000 (32 sets of 30000 cycles)
#   Exec. time (est) : 0:01:36
# Hung task detection not supported
#   (File /proc/sys/kernel/hung_task_timeout_secs not found)
# 16:57:15: Start of execution
# 16:57:18:  1/32: min:    1 avg:   1.0 max:    5
# 16:57:21:  2/32: min:    1 avg:   1.0 max:    4
# 16:57:24:  3/32: min:    1 avg:   1.0 max:    7
# 16:57:27:  4/32: min:    1 avg:   1.0 max:   14
# 16:57:30:  5/32: min:    1 avg:   1.0 max:   14
# 16:57:33:  6/32: min:    1 avg:   1.0 max:    5
# 16:57:36:  7/32: min:    1 avg:   1.0 max:    6
# 16:57:39:  8/32: min:    1 avg:   1.0 max:    5
# 16:57:42:  9/32: min:    1 avg:   1.0 max:    9
# 16:57:45: 10/32: min:    1 avg:   1.0 max:    5
# 16:57:48: 11/32: min:    1 avg:   1.0 max:    6
# 16:57:51: 12/32: min:    1 avg:   1.0 max:   15
# 16:57:54: 13/32: min:    1 avg:   1.0 max:    7
# 16:57:58: 14/32: min:    1 avg:   1.0 max:    7
# 16:58:01: 15/32: min:    1 avg:   1.0 max:   11
# 16:58:04: 16/32: min:    1 avg:   1.0 max:    8
# 16:58:07: 17/32: min:    1 avg:   1.0 max:   13
# 16:58:10: 18/32: min:    1 avg:   1.0 max:    6
# 16:58:13: 19/32: min:    1 avg:   1.0 max:    5
# 16:58:16: 20/32: min:    1 avg:   1.0 max:   12
# 16:58:19: 21/32: min:    1 avg:   1.0 max:   12
# 16:58:22: 22/32: min:    1 avg:   1.0 max:    6
# 16:58:25: 23/32: min:    1 avg:   1.0 max:   10
# 16:58:28: 24/32: min:    1 avg:   1.0 max:   13
# 16:58:31: 25/32: min:    1 avg:   1.0 max:    8
# 16:58:34: 26/32: min:    1 avg:   1.0 max:   16
# 16:58:37: 27/32: min:    1 avg:   1.0 max:   17
# 16:58:40: 28/32: min:    1 avg:   1.0 max:    6
# 16:58:44: 29/32: min:    1 avg:   1.0 max:    7
# 16:58:47: 30/32: min:    1 avg:   1.0 max:    5
# 16:58:50: 31/32: min:    1 avg:   1.0 max:   16
# 16:58:53: 32/32: min:    1 avg:   1.0 max:   15
# 16:58:53: Cyclictest completed. Actual execution time:0:01:38
# Min: 1 us
# Avg: 1.0 us
# Max: 17 us
# Max list: [4, 5, 11, 13, 15, 17]
# PASS

rt_bmark.intlat.no_stress [Min/us,Avg/us,Max/us]:
1,1.0,17
PASS: rt_bmark.intlat.no_stress

# ==============================================================================
#   Test case (2/6): rt_bmark.intlat.cpu
# ..............................................................................
# Starting stress(cpu)
#   Command: 'stress -c 8'
# Starting cyclictest
#   Command          : /opt/benchmarking/rt-tests/cyclictest -S -p 99 -q -i 100 -d 20 -l 30000
#   Number of cycles : 960000 (32 sets of 30000 cycles)
#   Exec. time (est) : 0:01:36
# 16:58:53: Start of execution
stress: info: [3306] dispatching hogs: 8 cpu, 0 io, 0 vm, 0 hdd
# 16:58:56:  1/32: min:    1 avg:   1.0 max:    7
# 16:58:59:  2/32: min:    1 avg:   1.0 max:   12
# 16:59:02:  3/32: min:    1 avg:   1.0 max:   14
# 16:59:05:  4/32: min:    1 avg:   1.0 max:   10
# 16:59:08:  5/32: min:    1 avg:   1.0 max:    9
# 16:59:11:  6/32: min:    1 avg:   1.0 max:   17
# 16:59:14:  7/32: min:    1 avg:   1.0 max:   17
# 16:59:18:  8/32: min:    1 avg:   1.0 max:   17
# 16:59:21:  9/32: min:    1 avg:   1.0 max:    6
# 16:59:24: 10/32: min:    1 avg:   1.0 max:   12
# 16:59:27: 11/32: min:    1 avg:   1.0 max:   16
# 16:59:30: 12/32: min:    1 avg:   1.0 max:   18
# 16:59:33: 13/32: min:    1 avg:   1.0 max:   17
# 16:59:36: 14/32: min:    1 avg:   1.0 max:   15
# 16:59:39: 15/32: min:    1 avg:   1.0 max:   17
# 16:59:43: 16/32: min:    1 avg:   1.0 max:   18
# 16:59:46: 17/32: min:    1 avg:   1.0 max:   18
# 16:59:49: 18/32: min:    1 avg:   1.0 max:   15
# 16:59:52: 19/32: min:    1 avg:   1.0 max:   19
# 16:59:55: 20/32: min:    1 avg:   1.0 max:    5
# 16:59:58: 21/32: min:    1 avg:   1.0 max:   16
# 17:00:01: 22/32: min:    1 avg:   1.0 max:   14
# 17:00:04: 23/32: min:    1 avg:   1.0 max:   19
# 17:00:07: 24/32: min:    1 avg:   1.0 max:   18
# 17:00:11: 25/32: min:    1 avg:   1.0 max:   13
# 17:00:14: 26/32: min:    1 avg:   1.0 max:   17
# 17:00:17: 27/32: min:    1 avg:   1.0 max:   13
# 17:00:20: 28/32: min:    1 avg:   1.0 max:   13
# 17:00:23: 29/32: min:    1 avg:   1.0 max:   18
# 17:00:26: 30/32: min:    1 avg:   1.0 max:    3
# 17:00:29: 31/32: min:    1 avg:   1.0 max:   11
# 17:00:32: 32/32: min:    1 avg:   1.0 max:   18
# 17:00:32: Cyclictest completed. Actual execution time:0:01:40
# Terminated stress
# Min: 1 us
# Avg: 1.0 us
# Max: 19 us
# Max list: [3, 12, 14, 17, 18, 19]
# PASS

rt_bmark.intlat.cpu [Min/us,Avg/us,Max/us]:
1,1.0,19
PASS: rt_bmark.intlat.cpu

# ==============================================================================
#   Test case (3/6): rt_bmark.intlat.hdd
# ..............................................................................
# Starting stress(hdd)
#   Command: 'stress -d 8 --hdd-bytes 20M'
# Starting cyclictest
#   Command          : /opt/benchmarking/rt-tests/cyclictest -S -p 99 -q -i 100 -d 20 -l 30000
#   Number of cycles : 960000 (32 sets of 30000 cycles)
#   Exec. time (est) : 0:01:36
# 17:00:32: Start of execution
stress: info: [3603] dispatching hogs: 0 cpu, 0 io, 0 vm, 8 hdd
# 17:00:35:  1/32: min:    1 avg:   1.7 max:   20
# 17:00:39:  2/32: min:    1 avg:   1.6 max:   19
# 17:00:42:  3/32: min:    1 avg:   1.7 max:   19
# 17:00:45:  4/32: min:    1 avg:   1.7 max:   17
# 17:00:48:  5/32: min:    1 avg:   1.7 max:   19
# 17:00:51:  6/32: min:    1 avg:   1.7 max:   14
# 17:00:54:  7/32: min:    1 avg:   1.5 max:   19
# 17:00:57:  8/32: min:    1 avg:   1.7 max:   18
# 17:01:00:  9/32: min:    1 avg:   1.7 max:   20
# 17:01:03: 10/32: min:    1 avg:   1.7 max:   18
# 17:01:06: 11/32: min:    1 avg:   1.7 max:   19
# 17:01:09: 12/32: min:    1 avg:   1.7 max:   18
# 17:01:13: 13/32: min:    1 avg:   1.7 max:   19
# 17:01:16: 14/32: min:    1 avg:   1.7 max:   20
# 17:01:19: 15/32: min:    1 avg:   1.7 max:   18
# 17:01:22: 16/32: min:    1 avg:   1.7 max:   20
# 17:01:25: 17/32: min:    1 avg:   1.7 max:   18
# 17:01:28: 18/32: min:    1 avg:   1.7 max:   16
# 17:01:31: 19/32: min:    1 avg:   1.7 max:   20
# 17:01:34: 20/32: min:    1 avg:   1.7 max:   19
# 17:01:37: 21/32: min:    1 avg:   1.7 max:   18
# 17:01:40: 22/32: min:    1 avg:   1.7 max:   19
# 17:01:43: 23/32: min:    1 avg:   1.7 max:   19
# 17:01:47: 24/32: min:    1 avg:   1.7 max:   19
# 17:01:50: 25/32: min:    1 avg:   1.7 max:   19
# 17:01:53: 26/32: min:    1 avg:   1.7 max:   19
# 17:01:56: 27/32: min:    1 avg:   1.7 max:   19
# 17:01:59: 28/32: min:    1 avg:   1.7 max:   17
# 17:02:02: 29/32: min:    1 avg:   1.7 max:   18
# 17:02:05: 30/32: min:    1 avg:   1.7 max:   19
# 17:02:08: 31/32: min:    1 avg:   1.7 max:   17
# 17:02:11: 32/32: min:    1 avg:   1.7 max:   18
# 17:02:11: Cyclictest completed. Actual execution time:0:01:39
# Terminated stress
# Min: 1 us
# Avg: 1.7 us
# Max: 20 us
# Max list: [14, 18, 19, 19, 20, 20]
# PASS

rt_bmark.intlat.hdd [Min/us,Avg/us,Max/us]:
1,1.7,20
PASS: rt_bmark.intlat.hdd

# ==============================================================================
#   Test case (4/6): rt_bmark.intlat.io
# ..............................................................................
# Starting stress(io)
#   Command: 'stress -i 8'
# Starting cyclictest
#   Command          : /opt/benchmarking/rt-tests/cyclictest -S -p 99 -q -i 100 -d 20 -l 30000
#   Number of cycles : 960000 (32 sets of 30000 cycles)
#   Exec. time (est) : 0:01:36
# 17:02:11: Start of execution
stress: info: [3900] dispatching hogs: 0 cpu, 8 io, 0 vm, 0 hdd
# 17:02:14:  1/32: min:    1 avg:   1.0 max:   19
# 17:02:17:  2/32: min:    1 avg:   1.0 max:    7
# 17:02:21:  3/32: min:    1 avg:   1.0 max:   11
# 17:02:24:  4/32: min:    1 avg:   1.0 max:    5
# 17:02:27:  5/32: min:    1 avg:   1.0 max:    4
# 17:02:30:  6/32: min:    1 avg:   1.0 max:    8
# 17:02:33:  7/32: min:    1 avg:   1.0 max:    5
# 17:02:36:  8/32: min:    1 avg:   1.0 max:   21
# 17:02:39:  9/32: min:    1 avg:   1.0 max:    4
# 17:02:42: 10/32: min:    1 avg:   1.0 max:    8
# 17:02:45: 11/32: min:    1 avg:   1.0 max:   11
# 17:02:48: 12/32: min:    1 avg:   1.0 max:    7
# 17:02:51: 13/32: min:    1 avg:   1.0 max:   13
# 17:02:54: 14/32: min:    1 avg:   1.0 max:    5
# 17:02:57: 15/32: min:    1 avg:   1.0 max:   14
# 17:03:00: 16/32: min:    1 avg:   1.0 max:    7
# 17:03:03: 17/32: min:    1 avg:   1.0 max:   17
# 17:03:07: 18/32: min:    1 avg:   1.0 max:    4
# 17:03:10: 19/32: min:    1 avg:   1.0 max:    7
# 17:03:13: 20/32: min:    1 avg:   1.0 max:    8
# 17:03:16: 21/32: min:    1 avg:   1.0 max:   11
# 17:03:19: 22/32: min:    1 avg:   1.0 max:    6
# 17:03:22: 23/32: min:    1 avg:   1.0 max:    4
# 17:03:25: 24/32: min:    1 avg:   1.0 max:    7
# 17:03:28: 25/32: min:    1 avg:   1.0 max:    8
# 17:03:31: 26/32: min:    1 avg:   1.0 max:   11
# 17:03:34: 27/32: min:    1 avg:   1.0 max:    8
# 17:03:37: 28/32: min:    1 avg:   1.0 max:   11
# 17:03:40: 29/32: min:    1 avg:   1.0 max:    6
# 17:03:43: 30/32: min:    1 avg:   1.0 max:   13
# 17:03:46: 31/32: min:    1 avg:   1.0 max:    8
# 17:03:50: 32/32: min:    1 avg:   1.0 max:   14
# 17:03:50: Cyclictest completed. Actual execution time:0:01:38
# Terminated stress
# Min: 1 us
# Avg: 1.0 us
# Max: 21 us
# Max list: [4, 7, 11, 14, 17, 21]
# PASS

rt_bmark.intlat.io [Min/us,Avg/us,Max/us]:
1,1.0,21
PASS: rt_bmark.intlat.io

# ==============================================================================
#   Test case (5/6): rt_bmark.intlat.vm
# ..............................................................................
# Starting stress(vm)
#   Command: 'stress -m 8 --vm-bytes 10M'
# Starting cyclictest
#   Command          : /opt/benchmarking/rt-tests/cyclictest -S -p 99 -q -i 100 -d 20 -l 30000
#   Number of cycles : 960000 (32 sets of 30000 cycles)
#   Exec. time (est) : 0:01:36
# 17:03:50: Start of execution
stress: info: [4197] dispatching hogs: 0 cpu, 0 io, 8 vm, 0 hdd
# 17:03:53:  1/32: min:    1 avg:   2.6 max:   22
# 17:03:56:  2/32: min:    1 avg:   2.5 max:   20
# 17:03:59:  3/32: min:    1 avg:   2.6 max:   20
# 17:04:02:  4/32: min:    1 avg:   2.4 max:   22
# 17:04:05:  5/32: min:    1 avg:   2.4 max:   20
# 17:04:08:  6/32: min:    1 avg:   2.5 max:   22
# 17:04:11:  7/32: min:    1 avg:   2.5 max:   22
# 17:04:14:  8/32: min:    1 avg:   2.7 max:   22
# 17:04:17:  9/32: min:    1 avg:   2.9 max:   23
# 17:04:21: 10/32: min:    1 avg:   2.5 max:   20
# 17:04:24: 11/32: min:    1 avg:   2.3 max:   18
# 17:04:27: 12/32: min:    1 avg:   2.6 max:   20
# 17:04:30: 13/32: min:    1 avg:   2.2 max:   19
# 17:04:33: 14/32: min:    1 avg:   2.5 max:   21
# 17:04:36: 15/32: min:    1 avg:   2.6 max:   21
# 17:04:39: 16/32: min:    1 avg:   2.5 max:   19
# 17:04:42: 17/32: min:    1 avg:   2.5 max:   18
# 17:04:45: 18/32: min:    1 avg:   2.5 max:   22
# 17:04:49: 19/32: min:    1 avg:   2.6 max:   19
# 17:04:52: 20/32: min:    1 avg:   2.4 max:   21
# 17:04:55: 21/32: min:    1 avg:   2.6 max:   19
# 17:04:58: 22/32: min:    1 avg:   2.5 max:   21
# 17:05:01: 23/32: min:    1 avg:   2.3 max:   19
# 17:05:04: 24/32: min:    1 avg:   2.6 max:   22
# 17:05:07: 25/32: min:    1 avg:   2.6 max:   20
# 17:05:10: 26/32: min:    1 avg:   2.6 max:   23
# 17:05:13: 27/32: min:    1 avg:   2.7 max:   22
# 17:05:17: 28/32: min:    1 avg:   2.5 max:   20
# 17:05:20: 29/32: min:    1 avg:   2.5 max:   22
# 17:05:23: 30/32: min:    1 avg:   2.5 max:   20
# 17:05:26: 31/32: min:    1 avg:   2.6 max:   22
# 17:05:29: 32/32: min:    1 avg:   2.6 max:   21
# 17:05:29: Cyclictest completed. Actual execution time:0:01:40
# Terminated stress
# Min: 1 us
# Avg: 2.5 us
# Max: 23 us
# Max list: [18, 20, 21, 22, 23, 23]
# PASS

rt_bmark.intlat.vm [Min/us,Avg/us,Max/us]:
1,2.5,23
PASS: rt_bmark.intlat.vm

# ==============================================================================
#   Test case (6/6): rt_bmark.intlat.full
# ..............................................................................
# Starting stress(io+cpu+hdd+vm)
#   Command: 'stress -i 8 -c 8 -d 8 --hdd-bytes 20M -m 8 --vm-bytes 10M'
# Starting cyclictest
#   Command          : /opt/benchmarking/rt-tests/cyclictest -S -p 99 -q -i 100 -d 20 -l 30000
#   Number of cycles : 960000 (32 sets of 30000 cycles)
#   Exec. time (est) : 0:01:36
# 17:05:29: Start of execution
stress: info: [4495] dispatching hogs: 8 cpu, 8 io, 8 vm, 8 hdd
# 17:05:32:  1/32: min:    1 avg:   1.5 max:   17
# 17:05:35:  2/32: min:    1 avg:   1.7 max:   16
# 17:05:38:  3/32: min:    1 avg:   1.5 max:   14
# 17:05:41:  4/32: min:    1 avg:   1.5 max:   18
# 17:05:45:  5/32: min:    1 avg:   1.4 max:   20
# 17:05:48:  6/32: min:    1 avg:   1.3 max:   17
# 17:05:51:  7/32: min:    1 avg:   1.7 max:   20
# 17:05:54:  8/32: min:    1 avg:   1.9 max:   19
# 17:05:57:  9/32: min:    1 avg:   1.9 max:   19
# 17:06:00: 10/32: min:    1 avg:   1.7 max:   20
# 17:06:03: 11/32: min:    1 avg:   1.7 max:   20
# 17:06:06: 12/32: min:    1 avg:   1.9 max:   19
# 17:06:10: 13/32: min:    1 avg:   1.9 max:   20
# 17:06:13: 14/32: min:    1 avg:   1.8 max:   19
# 17:06:16: 15/32: min:    1 avg:   2.0 max:   20
# 17:06:19: 16/32: min:    1 avg:   1.9 max:   21
# 17:06:22: 17/32: min:    1 avg:   1.9 max:   20
# 17:06:25: 18/32: min:    1 avg:   1.9 max:   21
# 17:06:28: 19/32: min:    1 avg:   1.6 max:   19
# 17:06:31: 20/32: min:    1 avg:   1.5 max:   20
# 17:06:34: 21/32: min:    1 avg:   1.6 max:   20
# 17:06:38: 22/32: min:    1 avg:   1.5 max:   20
# 17:06:41: 23/32: min:    1 avg:   1.6 max:   20
# 17:06:44: 24/32: min:    1 avg:   1.4 max:   19
# 17:06:47: 25/32: min:    1 avg:   1.9 max:   19
# 17:06:50: 26/32: min:    1 avg:   1.9 max:   20
# 17:06:53: 27/32: min:    1 avg:   1.9 max:   20
# 17:06:56: 28/32: min:    1 avg:   1.8 max:   19
# 17:06:59: 29/32: min:    1 avg:   1.9 max:   18
# 17:07:03: 30/32: min:    1 avg:   2.0 max:   19
# 17:07:06: 31/32: min:    1 avg:   1.9 max:   19
# 17:07:09: 32/32: min:    1 avg:   1.9 max:   19
# 17:07:09: Cyclictest completed. Actual execution time:0:01:40
# Terminated stress
# Min: 1 us
# Avg: 1.7 us
# Max: 21 us
# Max list: [14, 17, 18, 20, 21, 21]
# PASS

rt_bmark.intlat.full [Min/us,Avg/us,Max/us]:
1,1.7,21
PASS: rt_bmark.intlat.full

TGL-RVP Core i7-1185GRE - RT Benchmark

Click to toggle the results

# ==============================================================================
#   Test case (1/6): rt_bmark.intlat.no_stress
# ..............................................................................
# No stress requested
# Starting cyclictest
#   Command          : /opt/benchmarking/rt-tests/cyclictest -S -p 99 -q -i 100 -d 20 -l 30000
#   Number of cycles : 960000 (32 sets of 30000 cycles)
#   Exec. time (est) : 0:01:36
# Hung task detection not supported
#   (File /proc/sys/kernel/hung_task_timeout_secs not found)
# 16:43:12: Start of execution
# 16:43:15:  1/32: min:    1 avg:   1.0 max:    6
# 16:43:18:  2/32: min:    1 avg:   1.0 max:    6
# 16:43:21:  3/32: min:    1 avg:   1.0 max:    5
# 16:43:24:  4/32: min:    1 avg:   1.0 max:    4
# 16:43:28:  5/32: min:    1 avg:   1.0 max:    8
# 16:43:31:  6/32: min:    1 avg:   1.0 max:    5
# 16:43:34:  7/32: min:    1 avg:   1.0 max:    5
# 16:43:37:  8/32: min:    1 avg:   1.0 max:    4
# 16:43:40:  9/32: min:    1 avg:   1.0 max:    4
# 16:43:43: 10/32: min:    1 avg:   1.0 max:    6
# 16:43:46: 11/32: min:    1 avg:   1.0 max:    4
# 16:43:49: 12/32: min:    1 avg:   1.0 max:    5
# 16:43:52: 13/32: min:    1 avg:   1.0 max:    5
# 16:43:55: 14/32: min:    1 avg:   1.0 max:    5
# 16:43:58: 15/32: min:    1 avg:   1.0 max:    7
# 16:44:01: 16/32: min:    1 avg:   1.0 max:    7
# 16:44:04: 17/32: min:    1 avg:   1.0 max:    7
# 16:44:07: 18/32: min:    1 avg:   1.0 max:    5
# 16:44:10: 19/32: min:    1 avg:   1.0 max:    8
# 16:44:14: 20/32: min:    1 avg:   1.0 max:    9
# 16:44:17: 21/32: min:    1 avg:   1.0 max:    5
# 16:44:20: 22/32: min:    1 avg:   1.0 max:    5
# 16:44:23: 23/32: min:    1 avg:   1.0 max:    5
# 16:44:26: 24/32: min:    1 avg:   1.0 max:    6
# 16:44:29: 25/32: min:    1 avg:   1.0 max:    5
# 16:44:32: 26/32: min:    1 avg:   1.0 max:   10
# 16:44:35: 27/32: min:    1 avg:   1.0 max:    5
# 16:44:38: 28/32: min:    1 avg:   1.0 max:    6
# 16:44:41: 29/32: min:    1 avg:   1.0 max:    4
# 16:44:44: 30/32: min:    1 avg:   1.0 max:    4
# 16:44:47: 31/32: min:    1 avg:   1.0 max:    5
# 16:44:50: 32/32: min:    1 avg:   1.0 max:    4
# 16:44:50: Cyclictest completed. Actual execution time:0:01:38
# Min: 1 us
# Avg: 1.0 us
# Max: 10 us
# Max list: [4, 4, 5, 7, 8, 10]
# PASS

rt_bmark.intlat.no_stress [Min/us,Avg/us,Max/us]:
1,1.0,10
PASS: rt_bmark.intlat.no_stress

# ==============================================================================
#   Test case (2/6): rt_bmark.intlat.cpu
# ..............................................................................
# Starting stress(cpu)
#   Command: 'stress -c 4'
# Starting cyclictest
#   Command          : /opt/benchmarking/rt-tests/cyclictest -S -p 99 -q -i 100 -d 20 -l 30000
#   Number of cycles : 960000 (32 sets of 30000 cycles)
#   Exec. time (est) : 0:01:36
# 16:44:50: Start of execution
stress: info: [2405] dispatching hogs: 4 cpu, 0 io, 0 vm, 0 hdd
# 16:44:53:  1/32: min:    1 avg:   1.0 max:   13
# 16:44:57:  2/32: min:    1 avg:   1.0 max:    5
# 16:45:00:  3/32: min:    1 avg:   1.0 max:    5
# 16:45:03:  4/32: min:    1 avg:   1.0 max:    4
# 16:45:06:  5/32: min:    1 avg:   1.0 max:    6
# 16:45:09:  6/32: min:    1 avg:   1.0 max:    9
# 16:45:12:  7/32: min:    1 avg:   1.0 max:    5
# 16:45:15:  8/32: min:    1 avg:   1.0 max:    5
# 16:45:18:  9/32: min:    1 avg:   1.0 max:   13
# 16:45:21: 10/32: min:    1 avg:   1.0 max:    6
# 16:45:24: 11/32: min:    1 avg:   1.0 max:    5
# 16:45:28: 12/32: min:    1 avg:   1.0 max:    5
# 16:45:31: 13/32: min:    1 avg:   1.0 max:    5
# 16:45:34: 14/32: min:    1 avg:   1.0 max:    5
# 16:45:37: 15/32: min:    1 avg:   1.0 max:    4
# 16:45:40: 16/32: min:    1 avg:   1.0 max:    7
# 16:45:43: 17/32: min:    1 avg:   1.0 max:    5
# 16:45:46: 18/32: min:    1 avg:   1.0 max:    5
# 16:45:49: 19/32: min:    1 avg:   1.0 max:    5
# 16:45:52: 20/32: min:    1 avg:   1.0 max:    5
# 16:45:56: 21/32: min:    1 avg:   1.0 max:    5
# 16:45:59: 22/32: min:    1 avg:   1.0 max:    9
# 16:46:02: 23/32: min:    1 avg:   1.0 max:    5
# 16:46:05: 24/32: min:    1 avg:   1.0 max:    8
# 16:46:08: 25/32: min:    1 avg:   1.0 max:    8
# 16:46:11: 26/32: min:    1 avg:   1.0 max:    8
# 16:46:14: 27/32: min:    1 avg:   1.0 max:    6
# 16:46:17: 28/32: min:    1 avg:   1.0 max:   10
# 16:46:20: 29/32: min:    1 avg:   1.0 max:    4
# 16:46:23: 30/32: min:    1 avg:   1.0 max:    4
# 16:46:27: 31/32: min:    1 avg:   1.0 max:    4
# 16:46:30: 32/32: min:    1 avg:   1.0 max:   12
# 16:46:30: Cyclictest completed. Actual execution time:0:01:39
# Terminated stress
# Min: 1 us
# Avg: 1.0 us
# Max: 13 us
# Max list: [4, 4, 5, 9, 12, 13]
# PASS

rt_bmark.intlat.cpu [Min/us,Avg/us,Max/us]:
1,1.0,13
PASS: rt_bmark.intlat.cpu

# ==============================================================================
#   Test case (3/6): rt_bmark.intlat.hdd
# ..............................................................................
# Starting stress(hdd)
#   Command: 'stress -d 4 --hdd-bytes 20M'
# Starting cyclictest
#   Command          : /opt/benchmarking/rt-tests/cyclictest -S -p 99 -q -i 100 -d 20 -l 30000
#   Number of cycles : 960000 (32 sets of 30000 cycles)
#   Exec. time (est) : 0:01:36
# 16:46:30: Start of execution
stress: info: [2581] dispatching hogs: 0 cpu, 0 io, 0 vm, 4 hdd
# 16:46:33:  1/32: min:    1 avg:   1.3 max:   10
# 16:46:36:  2/32: min:    1 avg:   1.5 max:    8
# 16:46:39:  3/32: min:    1 avg:   1.5 max:    8
# 16:46:42:  4/32: min:    1 avg:   1.5 max:    7
# 16:46:45:  5/32: min:    1 avg:   1.5 max:    8
# 16:46:48:  6/32: min:    1 avg:   1.5 max:   11
# 16:46:51:  7/32: min:    1 avg:   1.5 max:    7
# 16:46:55:  8/32: min:    1 avg:   1.5 max:    8
# 16:46:58:  9/32: min:    1 avg:   1.8 max:    8
# 16:47:01: 10/32: min:    1 avg:   1.8 max:    8
# 16:47:04: 11/32: min:    1 avg:   1.5 max:    7
# 16:47:07: 12/32: min:    1 avg:   1.5 max:    8
# 16:47:10: 13/32: min:    1 avg:   1.5 max:    8
# 16:47:13: 14/32: min:    1 avg:   1.5 max:    7
# 16:47:16: 15/32: min:    1 avg:   1.5 max:   10
# 16:47:19: 16/32: min:    1 avg:   1.5 max:    7
# 16:47:23: 17/32: min:    1 avg:   1.5 max:    8
# 16:47:26: 18/32: min:    1 avg:   1.8 max:    9
# 16:47:29: 19/32: min:    1 avg:   1.5 max:    8
# 16:47:32: 20/32: min:    1 avg:   1.5 max:    8
# 16:47:35: 21/32: min:    1 avg:   1.5 max:    9
# 16:47:38: 22/32: min:    1 avg:   1.5 max:    8
# 16:47:41: 23/32: min:    1 avg:   1.5 max:   11
# 16:47:44: 24/32: min:    1 avg:   1.5 max:    8
# 16:47:47: 25/32: min:    1 avg:   1.5 max:    8
# 16:47:51: 26/32: min:    1 avg:   1.5 max:    7
# 16:47:54: 27/32: min:    1 avg:   1.5 max:    8
# 16:47:57: 28/32: min:    1 avg:   1.5 max:   12
# 16:48:00: 29/32: min:    1 avg:   1.5 max:    7
# 16:48:03: 30/32: min:    1 avg:   1.3 max:    6
# 16:48:06: 31/32: min:    1 avg:   1.2 max:    7
# 16:48:09: 32/32: min:    1 avg:   1.5 max:    8
# 16:48:09: Cyclictest completed. Actual execution time:0:01:40
# Terminated stress
# Min: 1 us
# Avg: 1.5 us
# Max: 12 us
# Max list: [6, 7, 8, 10, 11, 12]
# PASS

rt_bmark.intlat.hdd [Min/us,Avg/us,Max/us]:
1,1.5,12
PASS: rt_bmark.intlat.hdd

# ==============================================================================
#   Test case (4/6): rt_bmark.intlat.io
# ..............................................................................
# Starting stress(io)
#   Command: 'stress -i 4'
# Starting cyclictest
#   Command          : /opt/benchmarking/rt-tests/cyclictest -S -p 99 -q -i 100 -d 20 -l 30000
#   Number of cycles : 960000 (32 sets of 30000 cycles)
#   Exec. time (est) : 0:01:36
# 16:48:09: Start of execution
stress: info: [2756] dispatching hogs: 0 cpu, 4 io, 0 vm, 0 hdd
# 16:48:12:  1/32: min:    1 avg:   1.0 max:    7
# 16:48:15:  2/32: min:    1 avg:   1.0 max:    5
# 16:48:18:  3/32: min:    1 avg:   1.0 max:    5
# 16:48:21:  4/32: min:    1 avg:   1.0 max:    6
# 16:48:25:  5/32: min:    1 avg:   1.0 max:    5
# 16:48:28:  6/32: min:    1 avg:   1.0 max:    5
# 16:48:31:  7/32: min:    1 avg:   1.0 max:    6
# 16:48:34:  8/32: min:    1 avg:   1.0 max:    6
# 16:48:37:  9/32: min:    1 avg:   1.0 max:    6
# 16:48:40: 10/32: min:    1 avg:   1.0 max:    7
# 16:48:43: 11/32: min:    1 avg:   1.0 max:    6
# 16:48:46: 12/32: min:    1 avg:   1.0 max:    6
# 16:48:49: 13/32: min:    1 avg:   1.0 max:    6
# 16:48:52: 14/32: min:    1 avg:   1.0 max:    8
# 16:48:55: 15/32: min:    1 avg:   1.0 max:    6
# 16:48:58: 16/32: min:    1 avg:   1.0 max:    5
# 16:49:01: 17/32: min:    1 avg:   1.0 max:   11
# 16:49:04: 18/32: min:    1 avg:   1.0 max:    6
# 16:49:08: 19/32: min:    1 avg:   1.0 max:    9
# 16:49:11: 20/32: min:    1 avg:   1.0 max:    5
# 16:49:14: 21/32: min:    1 avg:   1.0 max:    6
# 16:49:17: 22/32: min:    1 avg:   1.0 max:    6
# 16:49:20: 23/32: min:    1 avg:   1.0 max:    6
# 16:49:23: 24/32: min:    1 avg:   1.0 max:    5
# 16:49:26: 25/32: min:    1 avg:   1.0 max:    5
# 16:49:29: 26/32: min:    1 avg:   1.0 max:    6
# 16:49:32: 27/32: min:    1 avg:   1.0 max:    5
# 16:49:35: 28/32: min:    1 avg:   1.0 max:    9
# 16:49:38: 29/32: min:    1 avg:   1.0 max:    6
# 16:49:41: 30/32: min:    1 avg:   1.0 max:    5
# 16:49:44: 31/32: min:    1 avg:   1.0 max:    5
# 16:49:47: 32/32: min:    1 avg:   1.0 max:    7
# 16:49:47: Cyclictest completed. Actual execution time:0:01:38
# Terminated stress
# Min: 1 us
# Avg: 1.0 us
# Max: 11 us
# Max list: [5, 5, 6, 7, 8, 11]
# PASS

rt_bmark.intlat.io [Min/us,Avg/us,Max/us]:
1,1.0,11
PASS: rt_bmark.intlat.io

# ==============================================================================
#   Test case (5/6): rt_bmark.intlat.vm
# ..............................................................................
# Starting stress(vm)
#   Command: 'stress -m 4 --vm-bytes 10M'
# Starting cyclictest
#   Command          : /opt/benchmarking/rt-tests/cyclictest -S -p 99 -q -i 100 -d 20 -l 30000
#   Number of cycles : 960000 (32 sets of 30000 cycles)
#   Exec. time (est) : 0:01:36
# 16:49:47: Start of execution
stress: info: [2933] dispatching hogs: 0 cpu, 0 io, 4 vm, 0 hdd
# 16:49:51:  1/32: min:    1 avg:   2.5 max:   11
# 16:49:54:  2/32: min:    1 avg:   2.5 max:    9
# 16:49:57:  3/32: min:    1 avg:   2.5 max:    9
# 16:50:00:  4/32: min:    1 avg:   2.5 max:    9
# 16:50:03:  5/32: min:    1 avg:   2.3 max:    9
# 16:50:06:  6/32: min:    1 avg:   2.5 max:    9
# 16:50:09:  7/32: min:    1 avg:   2.5 max:   10
# 16:50:12:  8/32: min:    1 avg:   2.5 max:    8
# 16:50:15:  9/32: min:    1 avg:   2.5 max:    9
# 16:50:18: 10/32: min:    1 avg:   2.5 max:    9
# 16:50:22: 11/32: min:    1 avg:   2.5 max:   10
# 16:50:25: 12/32: min:    1 avg:   2.5 max:    8
# 16:50:28: 13/32: min:    1 avg:   2.5 max:    7
# 16:50:31: 14/32: min:    1 avg:   2.0 max:   12
# 16:50:34: 15/32: min:    1 avg:   2.3 max:    9
# 16:50:37: 16/32: min:    1 avg:   2.3 max:   10
# 16:50:40: 17/32: min:    1 avg:   2.5 max:    9
# 16:50:43: 18/32: min:    1 avg:   2.5 max:   10
# 16:50:46: 19/32: min:    1 avg:   2.7 max:   11
# 16:50:50: 20/32: min:    1 avg:   2.5 max:   10
# 16:50:53: 21/32: min:    1 avg:   2.5 max:   10
# 16:50:56: 22/32: min:    1 avg:   2.5 max:   10
# 16:50:59: 23/32: min:    1 avg:   2.3 max:   10
# 16:51:02: 24/32: min:    1 avg:   2.5 max:   10
# 16:51:05: 25/32: min:    1 avg:   2.5 max:   10
# 16:51:08: 26/32: min:    1 avg:   2.3 max:   10
# 16:51:11: 27/32: min:    1 avg:   2.5 max:   10
# 16:51:14: 28/32: min:    1 avg:   2.2 max:   10
# 16:51:17: 29/32: min:    1 avg:   2.3 max:    9
# 16:51:21: 30/32: min:    1 avg:   2.7 max:    9
# 16:51:24: 31/32: min:    1 avg:   2.3 max:   10
# 16:51:27: 32/32: min:    1 avg:   2.5 max:   11
# 16:51:27: Cyclictest completed. Actual execution time:0:01:39
# Terminated stress
# Min: 1 us
# Avg: 2.5 us
# Max: 12 us
# Max list: [7, 9, 10, 11, 11, 12]
# PASS

rt_bmark.intlat.vm [Min/us,Avg/us,Max/us]:
1,2.5,12
PASS: rt_bmark.intlat.vm

# ==============================================================================
#   Test case (6/6): rt_bmark.intlat.full
# ..............................................................................
# Starting stress(io+cpu+hdd+vm)
#   Command: 'stress -i 4 -c 4 -d 4 --hdd-bytes 20M -m 4 --vm-bytes 10M'
# Starting cyclictest
#   Command          : /opt/benchmarking/rt-tests/cyclictest -S -p 99 -q -i 100 -d 20 -l 30000
#   Number of cycles : 960000 (32 sets of 30000 cycles)
#   Exec. time (est) : 0:01:36
# 16:51:27: Start of execution
stress: info: [3109] dispatching hogs: 4 cpu, 4 io, 4 vm, 4 hdd
# 16:51:30:  1/32: min:    1 avg:   1.5 max:   11
# 16:51:33:  2/32: min:    1 avg:   1.7 max:    7
# 16:51:36:  3/32: min:    1 avg:   2.0 max:   10
# 16:51:39:  4/32: min:    1 avg:   2.0 max:   15
# 16:51:42:  5/32: min:    1 avg:   1.7 max:    9
# 16:51:45:  6/32: min:    1 avg:   2.0 max:    9
# 16:51:49:  7/32: min:    1 avg:   2.0 max:   10
# 16:51:52:  8/32: min:    1 avg:   1.8 max:    9
# 16:51:55:  9/32: min:    1 avg:   2.0 max:   11
# 16:51:58: 10/32: min:    1 avg:   2.0 max:   12
# 16:52:01: 11/32: min:    1 avg:   2.0 max:   10
# 16:52:04: 12/32: min:    1 avg:   2.0 max:   10
# 16:52:07: 13/32: min:    1 avg:   2.0 max:    8
# 16:52:10: 14/32: min:    1 avg:   2.0 max:   10
# 16:52:13: 15/32: min:    1 avg:   1.8 max:   12
# 16:52:17: 16/32: min:    1 avg:   2.0 max:    9
# 16:52:20: 17/32: min:    1 avg:   1.7 max:    8
# 16:52:23: 18/32: min:    1 avg:   1.7 max:   10
# 16:52:26: 19/32: min:    1 avg:   2.0 max:   11
# 16:52:29: 20/32: min:    1 avg:   2.0 max:    9
# 16:52:32: 21/32: min:    1 avg:   2.0 max:    9
# 16:52:35: 22/32: min:    1 avg:   2.0 max:    9
# 16:52:38: 23/32: min:    1 avg:   1.7 max:    9
# 16:52:41: 24/32: min:    1 avg:   1.7 max:    9
# 16:52:45: 25/32: min:    1 avg:   2.0 max:    9
# 16:52:48: 26/32: min:    1 avg:   1.7 max:   13
# 16:52:51: 27/32: min:    1 avg:   2.0 max:    8
# 16:52:54: 28/32: min:    1 avg:   2.0 max:   10
# 16:52:57: 29/32: min:    1 avg:   1.7 max:   14
# 16:53:00: 30/32: min:    1 avg:   2.0 max:    9
# 16:53:03: 31/32: min:    1 avg:   2.0 max:    9
# 16:53:06: 32/32: min:    1 avg:   2.0 max:    9
# 16:53:06: Cyclictest completed. Actual execution time:0:01:40
# Terminated stress
# Min: 1 us
# Avg: 1.9 us
# Max: 15 us
# Max list: [7, 9, 9, 11, 14, 15]
# PASS

rt_bmark.intlat.full [Min/us,Avg/us,Max/us]:
1,1.9,15
PASS: rt_bmark.intlat.full

---

The following configuration was used:

• Core affinity = 3

• Priority = -20 (nice -n -20)

• Total loops = 100000

• Thread distance = 1

• Interval = 1000.

• SSH session (not using integrated GPU)

Vecow Core i7-8665UE - Cyclictest

Click to toggle the results

T: 0 ( 3418) P:99 I:1000 C: 100000 Min:      2 Act:    3 Avg:    3 Max:       6
T: 1 ( 3419) P:99 I:1001 C:  99906 Min:      2 Act:    3 Avg:    3 Max:      13
T: 2 ( 3420) P:99 I:1002 C:  99806 Min:      2 Act:    3 Avg:    3 Max:      14
T: 3 ( 3421) P:99 I:1003 C:  99706 Min:      2 Act:    3 Avg:    3 Max:      10

Maxtang Core i7-8665U - Cyclictest

Click to toggle results

T: 0 ( 3408) P:99 I:1000 C: 100000 Min:      2 Act:    2 Avg:    2 Max:       6
T: 1 ( 3409) P:99 I:1001 C:  99907 Min:      2 Act:    3 Avg:    2 Max:       5
T: 2 ( 3410) P:99 I:1002 C:  99807 Min:      2 Act:    2 Avg:    2 Max:       6
T: 3 ( 3411) P:99 I:1003 C:  99707 Min:      2 Act:    3 Avg:    2 Max:       6

Vecow Core i7-1185G7E - Cyclictest

Click to toggle the results

T: 0 ( 3239) P:99 I:1000 C: 100000 Min:      1 Act:    2 Avg:    1 Max:       5
T: 1 ( 3240) P:99 I:1001 C:  99909 Min:      1 Act:    2 Avg:    1 Max:       4
T: 2 ( 3241) P:99 I:1002 C:  99809 Min:      1 Act:    2 Avg:    1 Max:       7
T: 3 ( 3242) P:99 I:1003 C:  99709 Min:      1 Act:    2 Avg:    1 Max:       5

Karbon 700 Core i7-9700TE - Cyclictest

Click to toggle the results

T: 0 ( 4924) P:99 I:1000 C: 100000 Min:      1 Act:    1 Avg:    1 Max:       3
T: 1 ( 4925) P:99 I:1001 C:  99908 Min:      1 Act:    1 Avg:    1 Max:       3
T: 2 ( 4926) P:99 I:1002 C:  99808 Min:      1 Act:    1 Avg:    1 Max:       6
T: 3 ( 4927) P:99 I:1003 C:  99708 Min:      1 Act:    1 Avg:    1 Max:      13

TGL-RVP Core i7-1185GRE - Cyclictest

Click to toggle the results

T: 0 ( 3369) P:99 I:1000 C: 100000 Min:      1 Act:    2 Avg:    1 Max:       5
T: 1 ( 3370) P:99 I:1001 C:  99903 Min:      1 Act:    2 Avg:    1 Max:       4
T: 2 ( 3371) P:99 I:1002 C:  99803 Min:      1 Act:    2 Avg:    1 Max:       5
T: 3 ( 3372) P:99 I:1003 C:  99703 Min:      1 Act:    2 Avg:    1 Max:       5

LMbench Results

See also

See section LMbench for more information about this benchmark.

The following configuration was used:

• Core affinity ($CORE_AFFINITY) = 1

• Memory total ($MEMRD_SIZE) = 192M

• Stride size ($MEMRD_CHUNCKS) = 512

• SSH session (not using integrated GPU)

Vecow Core i7-8665UE - LMbench

Click to toggle results

"stride=512
0.00049 2.359
0.00098 2.359
0.00195 2.359
0.00293 2.359
0.00391 2.359
0.00586 2.359
0.00781 2.359
0.01172 2.359
0.01562 2.359
0.02344 2.359
0.03125 2.359
0.04688 7.078
0.06250 7.078
0.09375 11.045
0.12500 7.078
0.18750 10.011
0.25000 13.413
0.37500 20.488
0.50000 23.776
0.75000 25.009
1.00000 25.136
1.50000 25.096
2.00000 25.118
3.00000 25.118
4.00000 25.135
6.00000 28.468
8.00000 37.914
12.00000 53.805
16.00000 61.140
24.00000 68.016
32.00000 71.751
48.00000 74.659
64.00000 76.549
96.00000 77.195
128.00000 77.740
192.00000 78.673

Maxtang Core i7-8665U - LMbench

Click to toggle results

"stride=512
0.00049 2.111
0.00098 2.111
0.00195 2.111
0.00293 2.111
0.00391 2.111
0.00586 2.111
0.00781 2.111
0.01172 2.111
0.01562 2.111
0.02344 2.111
0.03125 2.111
0.04688 6.333
0.06250 6.333
0.09375 6.333
0.12500 7.607
0.18750 10.307
0.25000 11.749
0.37500 18.385
0.50000 20.662
0.75000 21.718
1.00000 21.886
1.50000 21.886
2.00000 21.902
3.00000 21.886
4.00000 21.884
6.00000 25.640
8.00000 32.996
12.00000 52.716
16.00000 63.182
24.00000 73.131
32.00000 77.758
48.00000 82.619
64.00000 84.340
96.00000 86.536
128.00000 87.539
192.00000 88.612

Vecow Core i7-1185G7E - LMbench

Click to toggle results

"stride=512
0.00049 1.790
0.00098 1.790
0.00195 1.790
0.00293 1.790
0.00391 1.790
0.00586 1.790
0.00781 1.790
0.01172 1.790
0.01562 1.790
0.02344 1.790
0.03125 1.790
0.04688 1.790
0.06250 5.150
0.09375 5.371
0.12500 5.371
0.18750 5.372
0.25000 5.393
0.37500 5.686
0.50000 5.686
0.75000 5.685
1.00000 6.077
1.50000 12.188
2.00000 16.938
3.00000 20.578
4.00000 24.451
6.00000 43.337
8.00000 56.489
12.00000 76.421
16.00000 85.466
24.00000 92.918
32.00000 95.774
48.00000 98.434
64.00000 99.758
96.00000 100.663
128.00000 101.108
192.00000 101.245

Karbon 700 Core i7-9700TE - LMbench

Click to toggle results

"stride=512
0.00049 1.179
0.00098 1.179
0.00195 1.179
0.00293 1.179
0.00391 1.179
0.00586 1.179
0.00781 1.179
0.01172 1.179
0.01562 1.179
0.02344 1.179
0.03125 1.179
0.04688 3.538
0.06250 3.538
0.09375 3.538
0.12500 3.538
0.18750 6.356
0.25000 8.001
0.37500 11.525
0.50000 12.406
0.75000 12.728
1.00000 13.921
1.50000 12.730
2.00000 12.722
3.00000 12.728
4.00000 12.722
6.00000 14.485
8.00000 14.668
12.00000 22.482
16.00000 31.753
24.00000 43.589
32.00000 49.313
48.00000 54.212
64.00000 56.538
96.00000 59.089
128.00000 61.755
192.00000 61.747

TGL-RVP Core i7-1185GRE - LMbench

Click to toggle results

"stride=512
0.00049 1.790
0.00098 1.790
0.00195 1.790
0.00293 1.790
0.00391 1.790
0.00586 1.790
0.00781 1.790
0.01172 1.790
0.01562 1.790
0.02344 1.790
0.03125 1.790
0.04688 1.790
0.06250 5.035
0.09375 5.371
0.12500 5.371
0.18750 5.371
0.25000 5.392
0.37500 5.685
0.50000 5.685
0.75000 5.685
1.00000 6.605
1.50000 11.610
2.00000 16.300
3.00000 19.143
4.00000 26.229
6.00000 40.735
8.00000 53.488
12.00000 72.704
16.00000 81.191
24.00000 88.611
32.00000 93.122
48.00000 94.206
64.00000 95.082
96.00000 97.493
128.00000 95.928
192.00000 95.885

Jitter Results

See also

See section Jitter for more information om this benchmark.

Attention

This benchmark utilizes Cache Allocation Technology (CAT) when present.

The following configuration was used:

• Core affinity = 3

• Priority = -20 nice -n -20

• Noisy Neighbor stress-ng affinity = 0

• CAT used to assign 0x0f to COS0

• CAT used to assign 0xf0 to COS1

• SSH session (not using integrated GPU)

Vecow Core i7-8665UE - Jitter

Click to toggle results

Attention

This benchmark utilizes CAT when present.

Linux Jitter testing program version 1.9
The pragram will execute a dummy function 80000 times
Display is updated every 20000 displayUpdate intervals
Thread affinity will be set to core_id:3
Timings are in CPU Core cycles
Inst_Min:    Minimum Excution time during the display update interval(default is ~1 second)
Inst_Max:    Maximum Excution time during the display update interval(default is ~1 second)
Inst_jitter: Jitter in the Excution time during rhe display update interval. This is the value of interest
last_Exec:   The Excution time of last iteration just before the display update
Abs_Min:     Absolute Minimum Excution time since the program started or statistics were reset
Abs_Max:     Absolute Maximum Excution time since the program started or statistics were reset
tmp:         Cumulative value calcualted by the dummy function
Interval:    Time interval between the display updates in Core Cycles
Sample No:   Sample number

   Inst_Min   Inst_Max   Inst_jitter last_Exec  Abs_min    Abs_max      tmp       Interval     Sample No
   187934     319135     131201     187944     187934     319135     789905408 3777324522          1     131201
   187934     305416     117482     187954     187934     319135    3333750784 3777682643          2     131201
   187934     303094     115160     187951     187934     319135    1582628864 3777717236          3     131201
   187934     306090     118156     187949     187934     319135    4126474240 3777442206          4     131201
   187934     308002     120068     261885     187934     319135    2375352320 3777519383          5     131201
   187934     306756     118822     187951     187934     319135     624230400 3777523330          6     131201
   187934     308163     120229     187951     187934     319135    3168075776 3777541182          7     131201
   187934     307914     119980     187950     187934     319135    1416953856 3777561029          8     131201
   187934     305404     117470     187949     187934     319135    3960799232 3777542412          9     131201
   187934     306023     118089     187946     187934     319135    2209677312 3777249200         10     131201
   187934     310013     122079     187942     187934     319135     458555392 3777495239         11     131201
   187934     310594     122660     187942     187934     319135    3002400768 3777385363         12     131201
   187934     311598     123664     187940     187934     319135    1251278848 3777346274         13     131201
   187934     309653     121719     187943     187934     319135    3795124224 3777400269         14     131201
   187934     304191     116257     187951     187934     319135    2044002304 3777181266         15     131201
   187934     312616     124682     187956     187934     319135     292880384 3777161402         16     131201
   187934     311242     123308     187952     187934     319135    2836725760 3777260707         17     131201
   187934     312912     124978     187947     187934     319135    1085603840 3777251819         18     131201
   187934     312287     124353     187943     187934     319135    3629449216 3776972857         19     131201
   187934     312009     124075     187950     187934     319135    1878327296 3777233950         20     131201
   187934     312617     124683     187955     187934     319135     127205376 3777025597         21     131201
   187934     306578     118644     187939     187934     319135    2671050752 3777191210         22     131201
   187934     309258     121324     187949     187934     319135     919928832 3777038263         23     131201
   187934     301303     113369     187939     187934     319135    3463774208 3777190228         24     131201
   187934     302375     114441     187940     187934     319135    1712652288 3777159364         25     131201
   187934     306829     118895     187950     187934     319135    4256497664 3777171002         26     131201
   187934     302624     114690     187952     187934     319135    2505375744 3776981074         27     131201
   187934     302970     115036     187952     187934     319135     754253824 3777400392         28     131201
   187934     303603     115669     187945     187934     319135    3298099200 3777503987         29     131201
   187934     304584     116650     187952     187934     319135    1546977280 3777374289         30     131201
   187934     303278     115344     187955     187934     319135    4090822656 3777278559         31     131201
   187934     305926     117992     187945     187934     319135    2339700736 3777436837         32     131201
   187934     304839     116905     187948     187934     319135     588578816 3777530922         33     131201
   187934     308084     120150     187946     187934     319135    3132424192 3777837873         34     131201
   187934     307487     119553     187947     187934     319135    1381302272 3777456940         35     131201
   187934     341321     153387     187945     187934     341321    3925147648 3777879464         36     153387
   187934     306209     118275     187947     187934     341321    2174025728 3777450921         37     153387
   187934     309673     121739     187945     187934     341321     422903808 3777874808         38     153387
   187934     335004     147070     187952     187934     341321    2966749184 3777550227         39     153387
   Inst_Min   Inst_Max   Inst_jitter last_Exec  Abs_min    Abs_max      tmp       Interval     Sample No
   187934     307357     119423     187950     187934     341321    1215627264 3777834344         40     153387
   187934     306237     118303     187949     187934     341321    3759472640 3777858557         41     153387
   187934     303331     115397     187949     187934     341321    2008350720 3777596527         42     153387
   187934     305312     117378     187953     187934     341321     257228800 3777672458         43     153387
   187934     305382     117448     187952     187934     341321    2801074176 3777732748         44     153387
   187934     307904     119970     187945     187934     341321    1049952256 3777488573         45     153387
   187934     307236     119302     187946     187934     341321    3593797632 3777523602         46     153387
   187934     307754     119820     187957     187934     341321    1842675712 3777648605         47     153387
   187934     308272     120338     187949     187934     341321      91553792 3777763673         48     153387
   187934     310553     122619     187949     187934     341321    2635399168 3777370733         49     153387
   187934     309367     121433     187941     187934     341321     884277248 3777751820         50     153387
   187934     306677     118743     187950     187934     341321    3428122624 3777452475         51     153387
   187934     306572     118638     187942     187934     341321    1677000704 3777608275         52     153387
   187934     309221     121287     187951     187934     341321    4220846080 3777556898         53     153387
   187934     309446     121512     187944     187934     341321    2469724160 3777625263         54     153387
   187934     307495     119561     187946     187934     341321     718602240 3777566307         55     153387
   187934     308912     120978     187948     187934     341321    3262447616 3777685641         56     153387
   187934     307821     119887     187942     187934     341321    1511325696 3777426355         57     153387
   187934     312968     125034     187946     187934     341321    4055171072 3777843547         58     153387
   187934     314764     126830     187944     187934     341321    2304049152 3777919869         59     153387
   187934     313934     126000     187950     187934     341321     552927232 3777763932         60     153387
   187934     322441     134507     187957     187934     341321    3096772608 3777716578         61     153387
   187934     345938     158004     187955     187934     345938    1345650688 3778040992         62     158004
   187934     314219     126285     187951     187934     345938    3889496064 3778059220         63     158004
   187934     351315     163381     187959     187934     351315    2138374144 3778415555         64     163381
   187934     354086     166152     187950     187934     354086     387252224 3778366202         65     166152
   187934     352742     164808     187952     187934     354086    2931097600 3778677580         66     166152
   187934     351605     163671     187955     187934     354086    1179975680 3778614557         67     166152
   187934     351139     163205     187940     187934     354086    3723821056 3778969061         68     166152
   187934     350806     162872     187954     187934     354086    1972699136 3778841764         69     166152
   187934     352241     164307     187941     187934     354086     221577216 3778651302         70     166152
   187934     352594     164660     187943     187934     354086    2765422592 3779116087         71     166152
   187934     353068     165134     187944     187934     354086    1014300672 3779119332         72     166152
   187934     351475     163541     187955     187934     354086    3558146048 3778843979         73     166152
   187934     351778     163844     187950     187934     354086    1807024128 3779062738         74     166152
   187934     352055     164121     187952     187934     354086      55902208 3778953680         75     166152
   187934     350873     162939     187949     187934     354086    2599747584 3779074434         76     166152
   187934     350802     162868     187951     187934     354086     848625664 3779226374         77     166152
   187934     351394     163460     187951     187934     354086    3392471040 3779250956         78     166152
   187934     352910     164976     187942     187934     354086    1641349120 3779544243         79     166152
   Inst_Min   Inst_Max   Inst_jitter last_Exec  Abs_min    Abs_max      tmp       Interval     Sample No
   187934     351059     163125     187957     187934     354086    4185194496 3779675787         80     166152
   187934     351292     163358     187945     187934     354086    2434072576 3779462770         81     166152
   187934     353221     165287     187944     187934     354086     682950656 3779275216         82     166152
   187934     350327     162393     187949     187934     354086    3226796032 3779556340         83     166152
   187934     352174     164240     187943     187934     354086    1475674112 3779451148         84     166152
   187934     351299     163365     187946     187934     354086    4019519488 3779282291         85     166152
   187934     350786     162852     187946     187934     354086    2268397568 3779438212         86     166152
   187934     353030     165096     187937     187934     354086     517275648 3779686395         87     166152
   187934     349781     161847     187949     187934     354086    3061121024 3779649285         88     166152
   187934     351133     163199     187939     187934     354086    1309999104 3779623523         89     166152
   187934     351189     163255     187947     187934     354086    3853844480 3779558803         90     166152
   187934     349845     161911     187953     187934     354086    2102722560 3779541381         91     166152
   187934     351102     163168     187952     187934     354086     351600640 3780022222         92     166152
   187934     349491     161557     187944     187934     354086    2895446016 3779951051         93     166152
   187934     349144     161210     187938     187934     354086    1144324096 3779941360         94     166152
   187934     350128     162194     187955     187934     354086    3688169472 3779921378         95     166152
   187934     349294     161360     187951     187934     354086    1937047552 3779894364         96     166152
   187934     349278     161344     187953     187934     354086     185925632 3780029097         97     166152
   187934     347673     159739     187951     187934     354086    2729771008 3780091663         98     166152
   187934     348236     160302     187953     187934     354086     978649088 3780071713         99     166152
   187934     348398     160464     187945     187934     354086    3522494464 3780162960        100     166152
   187934     350825     162891     187949     187934     354086    1771372544 3780079545        101     166152
   187934     349724     161790     187957     187934     354086      20250624 3779994964        102     166152
   187934     348444     160510     187944     187934     354086    2564096000 3779809734        103     166152
   187934     342498     154564     187957     187934     354086     812974080 3780041428        104     166152
   187934     345977     158043     187946     187934     354086    3356819456 3779988998        105     166152
   187934     347782     159848     187941     187934     354086    1605697536 3779756224        106     166152
   187934     348436     160502     187951     187934     354086    4149542912 3779741994        107     166152
   187934     323722     135788     187951     187934     354086    2398420992 3779768617        108     166152
   187934     323917     135983     187944     187934     354086     647299072 3779536583        109     166152
   187934     325469     137535     187951     187934     354086    3191144448 3779738466        110     166152
   187934     322718     134784     187946     187934     354086    1440022528 3779610870        111     166152
   187934     321968     134034     187938     187934     354086    3983867904 3779618628        112     166152
   187934     322160     134226     187953     187934     354086    2232745984 3779535472        113     166152
   187934     321560     133626     187953     187934     354086     481624064 3779455027        114     166152
   187934     322052     134118     187952     187934     354086    3025469440 3779308262        115     166152
   187934     317475     129541     187949     187934     354086    1274347520 3779440346        116     166152
   187934     321378     133444     187943     187934     354086    3818192896 3779542094        117     166152
   187934     318981     131047     187948     187934     354086    2067070976 3779048164        118     166152
   187934     320327     132393     187946     187934     354086     315949056 3779521496        119     166152
   Inst_Min   Inst_Max   Inst_jitter last_Exec  Abs_min    Abs_max      tmp       Interval     Sample No
   187934     318438     130504     187944     187934     354086    2859794432 3779208085        120     166152
   187934     318001     130067     187952     187934     354086    1108672512 3779345036        121     166152
   187934     319467     131533     187943     187934     354086    3652517888 3779652733        122     166152
   187934     335148     147214     187941     187934     354086    1901395968 3779331195        123     166152
   187934     315842     127908     187943     187934     354086     150274048 3779443526        124     166152
   187934     317110     129176     187950     187934     354086    2694119424 3779852155        125     166152
   187934     315361     127427     187955     187934     354086     942997504 3779837485        126     166152
   187934     314479     126545     187946     187934     354086    3486842880 3779748340        127     166152
   187934     315937     128003     187955     187934     354086    1735720960 3779908025        128     166152
   187934     314843     126909     187950     187934     354086    4279566336 3779558637        129     166152
   187934     313765     125831     187948     187934     354086    2528444416 3779631460        130     166152
   187934     313479     125545     187956     187934     354086     777322496 3779922159        131     166152
   187934     316187     128253     187954     187934     354086    3321167872 3779687461        132     166152
   187934     312187     124253     187946     187934     354086    1570045952 3779852018        133     166152
   187934     312616     124682     187942     187934     354086    4113891328 3779839003        134     166152
   187934     314866     126932     187952     187934     354086    2362769408 3779781427        135     166152
   187934     312633     124699     187950     187934     354086     611647488 3779795013        136     166152
   187934     312655     124721     187946     187934     354086    3155492864 3779606779        137     166152
   187934     313228     125294     187947     187934     354086    1404370944 3779539803        138     166152
   187934     310141     122207     187946     187934     354086    3948216320 3779533362        139     166152
   187934     312013     124079     187953     187934     354086    2197094400 3779536770        140     166152
   187934     312163     124229     187953     187934     354086     445972480 3779320196        141     166152
   187934     311305     123371     187948     187934     354086    2989817856 3779548632        142     166152
   187934     309136     121202     187947     187934     354086    1238695936 3779448689        143     166152
   187934     307922     119988     187949     187934     354086    3782541312 3779188854        144     166152
   187934     309536     121602     187953     187934     354086    2031419392 3779473410        145     166152
   187934     306179     118245     187945     187934     354086     280297472 3779390297        146     166152
   187934     305513     117579     187951     187934     354086    2824142848 3779034927        147     166152
   187934     305239     117305     187948     187934     354086    1073020928 3779410907        148     166152
   187934     305509     117575     187953     187934     354086    3616866304 3779307609        149     166152
   187934     316579     128645     187948     187934     354086    1865744384 3778942301        150     166152
   187934     306452     118518     187948     187934     354086     114622464 3779190287        151     166152
   187934     307082     119148     188149     187934     354086    2658467840 3779292177        152     166152
   187934     308714     120780     187950     187934     354086     907345920 3779125403        153     166152
   187934     315852     127918     187947     187934     354086    3451191296 3779121863        154     166152
   187935     307165     119230     187940     187934     354086    1700069376 3778991356        155     166152
   187934     310833     122899     187942     187934     354086    4243914752 3778805052        156     166152
   187934     310871     122937     187943     187934     354086    2492792832 3778986899        157     166152
   187934     309883     121949     187958     187934     354086     741670912 3778904906        158     166152
   187934     310204     122270     187954     187934     354086    3285516288 3778823573        159     166152
   Inst_Min   Inst_Max   Inst_jitter last_Exec  Abs_min    Abs_max      tmp       Interval     Sample No
   187934     328554     140620     187944     187934     354086    1534394368 3778962124        160     166152
   187934     306994     119060     187942     187934     354086    4078239744 3778736830        161     166152
   187934     313021     125087     187946     187934     354086    2327117824 3778755454        162     166152
   187934     311489     123555     187956     187934     354086     575995904 3778446263        163     166152
   187934     309513     121579     187948     187934     354086    3119841280 3778383835        164     166152
   187934     311641     123707     187946     187934     354086    1368719360 3778556979        165     166152
   187934     311315     123381     187944     187934     354086    3912564736 3778677918        166     166152
   187934     305689     117755     187950     187934     354086    2161442816 3778483827        167     166152
   187934     313198     125264     187949     187934     354086     410320896 3778673884        168     166152
   187934     309283     121349     187953     187934     354086    2954166272 3778856961        169     166152
   187934     309985     122051     187958     187934     354086    1203044352 3778561175        170     166152
   187934     310472     122538     187949     187934     354086    3746889728 3778570223        171     166152
   187934     312630     124696     187947     187934     354086    1995767808 3779006677        172     166152
   187934     307234     119300     187942     187934     354086     244645888 3778688246        173     166152
   187934     311673     123739     187948     187934     354086    2788491264 3778819178        174     166152
   187934     312910     124976     187958     187934     354086    1037369344 3779082715        175     166152
   187934     314150     126216     187940     187934     354086    3581214720 3779154409        176     166152
   187934     314775     126841     187946     187934     354086    1830092800 3778795326        177     166152
   187934     318449     130515     187949     187934     354086      78970880 3779067385        178     166152
   187934     314564     126630     187951     187934     354086    2622816256 3779166053        179     166152
   187934     313019     125085     187953     187934     354086     871694336 3779075379        180     166152
   187934     307415     119481     187949     187934     354086    3415539712 3779128871        181     166152
   187934     306794     118860     187956     187934     354086    1664417792 3778991297        182     166152
   187935     309880     121945     187945     187934     354086    4208263168 3779018095        183     166152
   187934     307671     119737     187943     187934     354086    2457141248 3779131833        184     166152
   187934     311294     123360     187941     187934     354086     706019328 3778683817        185     166152
   187934     320007     132073     187951     187934     354086    3249864704 3778978894        186     166152
   187934     317351     129417     187950     187934     354086    1498742784 3779123838        187     166152
   187934     319339     131405     187942     187934     354086    4042588160 3778776605        188     166152
   187934     302886     114952     187949     187934     354086    2291466240 3778975658        189     166152
   187934     316776     128842     187955     187934     354086     540344320 3778990777        190     166152
   187934     324678     136744     187951     187934     354086    3084189696 3778923920        191     166152
   187934     323555     135621     187944     187934     354086    1333067776 3778644179        192     166152
   187934     303006     115072     187940     187934     354086    3876913152 3778816953        193     166152
   187934     325449     137515     187946     187934     354086    2125791232 3778600888        194     166152
   187934     302675     114741     187950     187934     354086     374669312 3778655336        195     166152
   187934     311333     123399     187944     187934     354086    2918514688 3778596177        196     166152
   187934     304511     116577     187946     187934     354086    1167392768 3778569176        197     166152
   187934     306739     118805     187944     187934     354086    3711238144 3778605892        198     166152
   187934     307873     119939     187944     187934     354086    1960116224 3778556163        199     166152
   Inst_Min   Inst_Max   Inst_jitter last_Exec  Abs_min    Abs_max      tmp       Interval     Sample No
   187934     306685     118751     187950     187934     354086     208994304 3778408221        200     166152

Maxtang Core i7-8665U - Jitter

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Attention

This benchmark utilizes Cache Allocation Technology when present.

Linux Jitter testing program version 1.9
The pragram will execute a dummy function 80000 times
Display is updated every 20000 displayUpdate intervals
Thread affinity will be set to core_id:3
Timings are in CPU Core cycles
Inst_Min:    Minimum Excution time during the display update interval(default is ~1 second)
Inst_Max:    Maximum Excution time during the display update interval(default is ~1 second)
Inst_jitter: Jitter in the Excution time during rhe display update interval. This is the value of interest
last_Exec:   The Excution time of last iteration just before the display update
Abs_Min:     Absolute Minimum Excution time since the program started or statistics were reset
Abs_Max:     Absolute Maximum Excution time since the program started or statistics were reset
tmp:         Cumulative value calcualted by the dummy function
Interval:    Time interval between the display updates in Core Cycles
Sample No:   Sample number

   Inst_Min   Inst_Max   Inst_jitter last_Exec  Abs_min    Abs_max      tmp       Interval     Sample No
   178252     178682        430     178296     178252     178682     269811712 3568015362          1        430
   178252     179800       1548     178264     178252     179800    3350528000 3568055068          2       1548
   178252     179354       1102     178324     178252     179800    2136276992 3568049844          3       1548
   178252     179396       1144     178332     178252     179800     922025984 3568038992          4       1548
   178252     179196        944     178290     178252     179800    4002742272 3568044346          5       1548
   178252     179068        816     178268     178252     179800    2788491264 3568038112          6       1548
   178252     179478       1226     178268     178252     179800    1574240256 3568046456          7       1548
   178252     179362       1110     178332     178252     179800     359989248 3568050336          8       1548
   178252     179232        980     178328     178252     179800    3440705536 3568037716          9       1548
   178252     179424       1172     178310     178252     179800    2226454528 3568039096         10       1548
   178252     179108        856     178270     178252     179800    1012203520 3568040740         11       1548
   178252     179310       1058     178258     178252     179800    4092919808 3568045760         12       1548
   178252     179402       1150     178288     178252     179800    2878668800 3568038148         13       1548
   178252     179924       1672     178332     178252     179924    1664417792 3568052182         14       1672
   178252     179238        986     178284     178252     179924     450166784 3568045746         15       1672
   178252     179556       1304     178262     178252     179924    3530883072 3568048372         16       1672
   178252     179048        796     178318     178252     179924    2316632064 3568048688         17       1672
   178252     179910       1658     178334     178252     179924    1102381056 3568039610         18       1672
   178252     179226        974     178286     178252     179924    4183097344 3568049636         19       1672
   178252     179200        948     178260     178252     179924    2968846336 3568041362         20       1672
   178252     179376       1124     178274     178252     179924    1754595328 3568043818         21       1672
   178252     179204        952     178296     178252     179924     540344320 3568034752         22       1672
   178252     179194        942     178332     178252     179924    3621060608 3568046150         23       1672
   178252     179018        766     178318     178252     179924    2406809600 3568040926         24       1672
   178252     178880        628     178270     178252     179924    1192558592 3568044146         25       1672
   178252     179768       1516     178262     178252     179924    4273274880 3568043180         26       1672
   178252     178876        624     178292     178252     179924    3059023872 3568041746         27       1672
   178252     179742       1490     178326     178252     179924    1844772864 3568039254         28       1672
   178252     179960       1708     178322     178252     179960     630521856 3568045162         29       1708
   178252     179546       1294     178294     178252     179960    3711238144 3568038466         30       1708
   178252     179214        962     178266     178252     179960    2496987136 3568038982         31       1708
   178252     179434       1182     178272     178252     179960    1282736128 3568047934         32       1708
   178252     179560       1308     178314     178252     179960      68485120 3568042100         33       1708
   178252     179246        994     178326     178252     179960    3149201408 3568046894         34       1708
   178252     179410       1158     178282     178252     179960    1934950400 3568043652         35       1708
   178252     179238        986     178262     178252     179960     720699392 3568043070         36       1708
   178252     179360       1108     178276     178252     179960    3801415680 3568040018         37       1708
   178252     179576       1324     178320     178252     179960    2587164672 3568043902         38       1708
   178252     179122        870     178326     178252     179960    1372913664 3568044050         39       1708
   Inst_Min   Inst_Max   Inst_jitter last_Exec  Abs_min    Abs_max      tmp       Interval     Sample No
   178252     178994        742     178304     178252     179960     158662656 3568075850         40       1708
   178252     179504       1252     178276     178252     179960    3239378944 3568068648         41       1708
   178252     179064        812     178260     178252     179960    2025127936 3568037728         42       1708
   178252     179408       1156     178278     178252     179960     810876928 3568045154         43       1708
   178252     179212        960     178320     178252     179960    3891593216 3568043492         44       1708
   178252     179234        982     178332     178252     179960    2677342208 3568040016         45       1708
   178252     179206        954     178318     178252     179960    1463091200 3568037558         46       1708
   178252     179244        992     178268     178252     179960     248840192 3568045670         47       1708
   178252     179398       1146     178282     178252     179960    3329556480 3568049962         48       1708
   178252     179052        800     178304     178252     179960    2115305472 3568036468         49       1708
   178252     179418       1166     178328     178252     179960     901054464 3568049100         50       1708
   178252     179026        774     178306     178252     179960    3981770752 3568037972         51       1708
   178252     179492       1240     178258     178252     179960    2767519744 3568050684         52       1708
   178252     179368       1116     178290     178252     179960    1553268736 3568044584         53       1708
   178252     179226        974     178334     178252     179960     339017728 3568046304         54       1708
   178252     179002        750     178310     178252     179960    3419734016 3568042434         55       1708
   178252     179748       1496     178268     178252     179960    2205483008 3568044750         56       1708
   178252     179168        916     178260     178252     179960     991232000 3568044256         57       1708
   178252     179420       1168     178306     178252     179960    4071948288 3568043628         58       1708
   178252     179234        982     178328     178252     179960    2857697280 3568042134         59       1708
   178252     179736       1484     178322     178252     179960    1643446272 3568038414         60       1708
   178252     179306       1054     178266     178252     179960     429195264 3568046388         61       1708
   178252     179758       1506     178260     178252     179960    3509911552 3568042724         62       1708
   178252     179774       1522     178302     178252     179960    2295660544 3568042778         63       1708
   178252     179030        778     178320     178252     179960    1081409536 3568036578         64       1708
   178252     179402       1150     178324     178252     179960    4162125824 3568047076         65       1708
   178252     178990        738     178272     178252     179960    2947874816 3568045054         66       1708
   178252     179202        950     178260     178252     179960    1733623808 3568044718         67       1708
   178252     179400       1148     178310     178252     179960     519372800 3568046694         68       1708
   178252     179732       1480     178332     178252     179960    3600089088 3568041366         69       1708
   178252     179232        980     178286     178252     179960    2385838080 3568051194         70       1708
   178252     179386       1134     178258     178252     179960    1171587072 3568042016         71       1708
   178252     179380       1128     178286     178252     179960    4252303360 3568043794         72       1708
   178252     179430       1178     178320     178252     179960    3038052352 3568040126         73       1708
   178252     179894       1642     178328     178252     179960    1823801344 3568044776         74       1708
   178252     179216        964     178304     178252     179960     609550336 3568038408         75       1708
   178252     178994        742     178274     178252     179960    3690266624 3568037436         76       1708
   178252     179426       1174     178262     178252     179960    2476015616 3568049012         77       1708
   178252     179554       1302     178320     178252     179960    1261764608 3568048490         78       1708
   178252     179390       1138     178326     178252     179960      47513600 3568040454         79       1708
   Inst_Min   Inst_Max   Inst_jitter last_Exec  Abs_min    Abs_max      tmp       Interval     Sample No
   178252     179890       1638     178266     178252     179960    3128229888 3568051808         80       1708
   178252     179374       1122     178260     178252     179960    1913978880 3568041424         81       1708
   178252     179232        980     178292     178252     179960     699727872 3568042268         82       1708
   178252     179556       1304     178326     178252     179960    3780444160 3568043620         83       1708
   178252     179252       1000     178320     178252     179960    2566193152 3568044014         84       1708
   178252     179532       1280     178272     178252     179960    1351942144 3568043584         85       1708
   178252     179372       1120     178264     178252     179960     137691136 3568045862         86       1708
   178252     179004        752     178324     178252     179960    3218407424 3568048280         87       1708
   178252     179070        818     178326     178252     179960    2004156416 3568046190         88       1708
   178252     179390       1138     178280     178252     179960     789905408 3568043484         89       1708
   178252     179378       1126     178270     178252     179960    3870621696 3568049450         90       1708
   178252     179208        956     178282     178252     179960    2656370688 3568035366         91       1708
   178252     179066        814     178326     178252     179960    1442119680 3568046012         92       1708
   178252     179544       1292     178330     178252     179960     227868672 3568034638         93       1708
   178252     179202        950     178306     178252     179960    3308584960 3568041782         94       1708
   178252     179206        954     178270     178252     179960    2094333952 3568042962         95       1708
   178252     179264       1012     178272     178252     179960     880082944 3568047954         96       1708
   178252     179420       1168     178318     178252     179960    3960799232 3568042582         97       1708
   178252     179582       1330     178330     178252     179960    2746548224 3568042926         98       1708
   178252     179328       1076     178294     178252     179960    1532297216 3568043866         99       1708
   178252     179488       1236     178258     178252     179960     318046208 3568047978        100       1708
   178252     179236        984     178292     178252     179960    3398762496 3568045516        101       1708
   178252     179236        984     178328     178252     179960    2184511488 3568043196        102       1708
   178252     179246        994     178320     178252     179960     970260480 3568043136        103       1708
   178252     179052        800     178268     178252     179960    4050976768 3568045904        104       1708
   178252     179400       1148     178286     178252     179960    2836725760 3568051102        105       1708
   178252     179224        972     178326     178252     179960    1622474752 3568041586        106       1708
   178252     179408       1156     178328     178252     179960     408223744 3568040638        107       1708
   178252     179178        926     178312     178252     179960    3488940032 3568037716        108       1708
   178252     179372       1120     178266     178252     179960    2274689024 3568042686        109       1708
   178252     179420       1168     178258     178252     179960    1060438016 3568046170        110       1708
   178252     179224        972     178298     178252     179960    4141154304 3568040838        111       1708
   178252     179278       1026     178330     178252     179960    2926903296 3568042510        112       1708
   178252     179032        780     178306     178252     179960    1712652288 3568046684        113       1708
   178252     179216        964     178260     178252     179960     498401280 3568045350        114       1708
   178252     179242        990     178270     178252     179960    3579117568 3568042220        115       1708
   178252     179174        922     178300     178252     179960    2364866560 3568039552        116       1708
   178252     179348       1096     178326     178252     179960    1150615552 3568037812        117       1708
   178252     179046        794     178330     178252     179960    4231331840 3568038838        118       1708
   178252     179474       1222     178288     178252     179960    3017080832 3568046474        119       1708
   Inst_Min   Inst_Max   Inst_jitter last_Exec  Abs_min    Abs_max      tmp       Interval     Sample No
   178252     179182        930     178256     178252     179960    1802829824 3568041552        120       1708
   178252     179064        812     178328     178252     179960     588578816 3568072580        121       1708
   178252     179198        946     178284     178252     179960    3669295104 3568042974        122       1708
   178252     179800       1548     178260     178252     179960    2455044096 3568046194        123       1708
   178252     179238        986     178272     178252     179960    1240793088 3568038348        124       1708
   178252     180278       2026     178332     178252     180278      26542080 3568049228        125       2026
   178252     179508       1256     178316     178252     180278    3107258368 3568043738        126       2026
   178252     179060        808     178286     178252     180278    1893007360 3568039608        127       2026
   178252     179564       1312     178256     178252     180278     678756352 3568044142        128       2026
   178252     179358       1106     178274     178252     180278    3759472640 3568039930        129       2026
   178252     179232        980     178312     178252     180278    2545221632 3568040896        130       2026
   178252     179044        792     178328     178252     180278    1330970624 3568041570        131       2026
   178252     179226        974     178290     178252     180278     116719616 3568047806        132       2026
   178252     178980        728     178258     178252     180278    3197435904 3568040676        133       2026
   178252     179618       1366     178282     178252     180278    1983184896 3568048048        134       2026
   178252     179054        802     178312     178252     180278     768933888 3568038650        135       2026
   178252     179042        790     178332     178252     180278    3849650176 3568044490        136       2026
   178252     179358       1106     178292     178252     180278    2635399168 3568044316        137       2026
   178252     179728       1476     178260     178252     180278    1421148160 3568041488        138       2026
   178252     179616       1364     178262     178252     180278     206897152 3568039514        139       2026
   178252     179468       1216     178308     178252     180278    3287613440 3568043482        140       2026
   178252     179428       1176     178322     178252     180278    2073362432 3568051780        141       2026
   178252     179246        994     178302     178252     180278     859111424 3568036134        142       2026
   178252     179396       1144     178258     178252     180278    3939827712 3568047898        143       2026
   178252     179396       1144     178268     178252     180278    2725576704 3568040192        144       2026
   178252     179532       1280     178316     178252     180278    1511325696 3568043758        145       2026
   178252     179366       1114     178336     178252     180278     297074688 3568041926        146       2026
   178252     178880        628     178310     178252     180278    3377790976 3568040740        147       2026
   178252     179172        920     178282     178252     180278    2163539968 3568036980        148       2026
   178252     179424       1172     178258     178252     180278     949288960 3568046594        149       2026
   178252     179332       1080     178288     178252     180278    4030005248 3568041684        150       2026
   178252     179392       1140     178326     178252     180278    2815754240 3568042010        151       2026
   178252     179292       1040     178322     178252     180278    1601503232 3568044996        152       2026
   178252     179102        850     178274     178252     180278     387252224 3568043894        153       2026
   178252     179178        926     178262     178252     180278    3467968512 3568043748        154       2026
   178252     179384       1132     178282     178252     180278    2253717504 3568039452        155       2026
   178252     179464       1212     178324     178252     180278    1039466496 3568042880        156       2026
   178252     179548       1296     178326     178252     180278    4120182784 3568043964        157       2026
   178252     179584       1332     178262     178252     180278    2905931776 3568052712        158       2026
   178252     179236        984     178266     178252     180278    1691680768 3568039640        159       2026
   Inst_Min   Inst_Max   Inst_jitter last_Exec  Abs_min    Abs_max      tmp       Interval     Sample No
   178252     179062        810     178306     178252     180278     477429760 3568043172        160       2026
   178252     179234        982     178336     178252     180278    3558146048 3568047434        161       2026
   178252     179508       1256     178304     178252     180278    2343895040 3568040626        162       2026
   178252     179168        916     178262     178252     180278    1129644032 3568042934        163       2026
   178252     179198        946     178266     178252     180278    4210360320 3568042354        164       2026
   178252     179222        970     178290     178252     180278    2996109312 3568038492        165       2026
   178252     179064        812     178322     178252     180278    1781858304 3568038950        166       2026
   178252     179612       1360     178318     178252     180278     567607296 3568049032        167       2026
   178252     179178        926     178284     178252     180278    3648323584 3568040070        168       2026
   178252     179092        840     178256     178252     180278    2434072576 3568039652        169       2026
   178252     179062        810     178272     178252     180278    1219821568 3568042224        170       2026
   178252     179544       1292     178324     178252     180278       5570560 3568046058        171       2026
   178252     179600       1348     178326     178252     180278    3086286848 3568043906        172       2026
   178252     179062        810     178284     178252     180278    1872035840 3568043442        173       2026
   178252     180528       2276     178256     178252     180528     657784832 3568045388        174       2276
   178252     179738       1486     178276     178252     180528    3738501120 3568039822        175       2276
   178252     179202        950     178328     178252     180528    2524250112 3568047872        176       2276
   178252     179028        776     178308     178252     180528    1309999104 3568045086        177       2276
   178252     179782       1530     178268     178252     180528      95748096 3568042894        178       2276
   178252     179588       1336     178256     178252     180528    3176464384 3568039108        179       2276
   178252     179188        936     178272     178252     180528    1962213376 3568039972        180       2276
   178252     179432       1180     178312     178252     180528     747962368 3568040720        181       2276
   178252     180330       2078     178334     178252     180528    3828678656 3568043802        182       2276
   178252     179238        986     178296     178252     180528    2614427648 3568044294        183       2276
   178252     179374       1122     178260     178252     180528    1400176640 3568042138        184       2276
   178252     179176        924     178288     178252     180528     185925632 3568049826        185       2276
   178252     180280       2028     178330     178252     180528    3266641920 3568042876        186       2276
   178252     179416       1164     178320     178252     180528    2052390912 3568042252        187       2276
   178252     179434       1182     178282     178252     180528     838139904 3568042690        188       2276
   178252     179178        926     178258     178252     180528    3918856192 3568039580        189       2276
   178252     179692       1440     178298     178252     180528    2704605184 3568051216        190       2276
   178252     180032       1780     178324     178252     180528    1490354176 3568051908        191       2276
   178252     179548       1296     178260     178252     180528     276103168 3568053422        192       2276
   178252     179934       1682     178270     178252     180528    3356819456 3568042888        193       2276
   178252     179414       1162     178330     178252     180528    2142568448 3568049166        194       2276
   178252     178986        734     178322     178252     180528     928317440 3568041146        195       2276
   178252     178984        732     178270     178252     180528    4009033728 3568047048        196       2276
   178252     179612       1360     178260     178252     180528    2794782720 3568042676        197       2276
   178252     179196        944     178270     178252     180528    1580531712 3568035964        198       2276
   178252     179312       1060     178294     178252     180528     366280704 3568036408        199       2276
   Inst_Min   Inst_Max   Inst_jitter last_Exec  Abs_min    Abs_max      tmp       Interval     Sample No
   178252     179578       1326     178258     178252     180528    3446996992 3568084032        200       2276

Vecow Core i7-1185G7E - Jitter

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Attention

This benchmark utilizes CAT when present.

Linux Jitter testing program version 1.9
The pragram will execute a dummy function 80000 times
Display is updated every 20000 displayUpdate intervals
Thread affinity will be set to core_id:3
Timings are in CPU Core cycles
Inst_Min:    Minimum Excution time during the display update interval(default is ~1 second)
Inst_Max:    Maximum Excution time during the display update interval(default is ~1 second)
Inst_jitter: Jitter in the Excution time during rhe display update interval. This is the value of interest
last_Exec:   The Excution time of last iteration just before the display update
Abs_Min:     Absolute Minimum Excution time since the program started or statistics were reset
Abs_Max:     Absolute Maximum Excution time since the program started or statistics were reset
tmp:         Cumulative value calcualted by the dummy function
Interval:    Time interval between the display updates in Core Cycles
Sample No:   Sample number

   Inst_Min   Inst_Max   Inst_jitter last_Exec  Abs_min    Abs_max      tmp       Interval     Sample No
   160547     162092       1545     160570     160547     162092    3288334336 3214533818          1       1545
   160548     162220       1672     160598     160547     162220    1140850688 3214587213          2       1672
   160547     162257       1710     160576     160547     162257    3288334336 3214516089          3       1710
   160547     161713       1166     160569     160547     162257    1140850688 3214515612          4       1710
   160547     162273       1726     160607     160547     162273    3288334336 3214518229          5       1726
   160547     161882       1335     160580     160547     162273    1140850688 3214541324          6       1726
   160548     161930       1382     160592     160547     162273    3288334336 3214519628          7       1726
   160547     161658       1111     160554     160547     162273    1140850688 3214507834          8       1726
   160548     161506        958     160609     160547     162273    3288334336 3214525800          9       1726
   160547     161095        548     160572     160547     162273    1140850688 3214510934         10       1726
   160548     161131        583     160600     160547     162273    3288334336 3214552694         11       1726
   160548     162090       1542     160602     160547     162273    1140850688 3214553121         12       1726
   160548     161448        900     160565     160547     162273    3288334336 3214543443         13       1726
   160547     163096       2549     160602     160547     163096    1140850688 3214522726         14       2549
   160547     161547       1000     160555     160547     163096    3288334336 3214523612         15       2549
   160547     162400       1853     160568     160547     163096    1140850688 3214550941         16       2549
   160547     162303       1756     160608     160547     163096    3288334336 3214539177         17       2549
   160548     162157       1609     160568     160547     163096    1140850688 3214598526         18       2549
   160548     161888       1340     160567     160547     163096    3288334336 3214508069         19       2549
   160547     161724       1177     160579     160547     163096    1140850688 3214539181         20       2549
   160548     161828       1280     160594     160547     163096    3288334336 3214532137         21       2549
   160548     162518       1970     160608     160547     163096    1140850688 3214491673         22       2549
   160547     161172        625     160606     160547     163096    3288334336 3214489018         23       2549
   160548     164021       3473     160576     160547     164021    1140850688 3214543178         24       3473
   160547     161427        880     160608     160547     164021    3288334336 3214507177         25       3473
   160547     162449       1902     160575     160547     164021    1140850688 3214505757         26       3473
   160548     162524       1976     160588     160547     164021    3288334336 3214526350         27       3473
   160548     162277       1729     160552     160547     164021    1140850688 3214541327         28       3473
   160548     161677       1129     160587     160547     164021    3288334336 3214595727         29       3473
   160547     165069       4522     160574     160547     165069    1140850688 3214527806         30       4522
   160547     161460        913     160568     160547     165069    3288334336 3214512646         31       4522
   160547     161476        929     160586     160547     165069    1140850688 3214531135         32       4522
   160547     162192       1645     160568     160547     165069    3288334336 3214520378         33       4522
   160547     161912       1365     160555     160547     165069    1140850688 3214550587         34       4522
   160548     161894       1346     160567     160547     165069    3288334336 3214501215         35       4522
   160548     161155        607     160604     160547     165069    1140850688 3214514433         36       4522
   160547     162579       2032     160604     160547     165069    3288334336 3214561328         37       4522
   160548     161127        579     160569     160547     165069    1140850688 3214518711         38       4522
   160547     162025       1478     160579     160547     165069    3288334336 3214515444         39       4522
   Inst_Min   Inst_Max   Inst_jitter last_Exec  Abs_min    Abs_max      tmp       Interval     Sample No
   160548     161277        729     160574     160547     165069    1140850688 3214532482         40       4522
   160548     161752       1204     160604     160547     165069    3288334336 3214534375         41       4522
   160547     162538       1991     160563     160547     165069    1140850688 3214523973         42       4522
   160548     161880       1332     160590     160547     165069    3288334336 3214519455         43       4522
   160548     161198        650     160604     160547     165069    1140850688 3214503406         44       4522
   160548     161586       1038     160555     160547     165069    3288334336 3214524950         45       4522
   160548     162972       2424     160579     160547     165069    1140850688 3214496490         46       4522
   160547     162550       2003     160584     160547     165069    3288334336 3214526328         47       4522
   160548     161164        616     160592     160547     165069    1140850688 3214536251         48       4522
   160548     161462        914     160572     160547     165069    3288334336 3214522225         49       4522
   160547     161975       1428     160596     160547     165069    1140850688 3214530060         50       4522
   160548     161555       1007     160570     160547     165069    3288334336 3214556209         51       4522
   160547     162316       1769     160556     160547     165069    1140850688 3214559607         52       4522
   160549     162743       2194     160590     160547     165069    3288334336 3214534359         53       4522
   160548     162086       1538     160569     160547     165069    1140850688 3214523480         54       4522
   160547     161504        957     160582     160547     165069    3288334336 3214531397         55       4522
   160548     164664       4116     160606     160547     165069    1140850688 3214545579         56       4522
   160548     161972       1424     160584     160547     165069    3288334336 3214595823         57       4522
   160548     161411        863     160562     160547     165069    1140850688 3214515491         58       4522
   160548     161792       1244     160598     160547     165069    3288334336 3214525265         59       4522
   160547     160867        320     160568     160547     165069    1140850688 3214531155         60       4522
   160547     162470       1923     160604     160547     165069    3288334336 3214517024         61       4522
   160548     161449        901     160600     160547     165069    1140850688 3214485997         62       4522
   160548     161784       1236     160554     160547     165069    3288334336 3214513980         63       4522
   160547     162447       1900     160608     160547     165069    1140850688 3214526434         64       4522
   160547     162622       2075     160556     160547     165069    3288334336 3214519415         65       4522
   160548     162403       1855     160579     160547     165069    1140850688 3214509853         66       4522
   160547     161117        570     160555     160547     165069    3288334336 3214466782         67       4522
   160547     161936       1389     160604     160547     165069    1140850688 3214526714         68       4522
   160549     161878       1329     160559     160547     165069    3288334336 3214599715         69       4522
   160547     164891       4344     160598     160547     165069    1140850688 3214543799         70       4522
   160547     161230        683     160556     160547     165069    3288334336 3214516748         71       4522
   160547     161281        734     160602     160547     165069    1140850688 3214516340         72       4522
   160548     161330        782     160582     160547     165069    3288334336 3214510052         73       4522
   160548     161419        871     160569     160547     165069    1140850688 3214489959         74       4522
   160547     162678       2131     160555     160547     165069    3288334336 3214502927         75       4522
   160547     161721       1174     160562     160547     165069    1140850688 3214554108         76       4522
   160547     161656       1109     160590     160547     165069    3288334336 3214521902         77       4522
   160548     162323       1775     160564     160547     165069    1140850688 3214526133         78       4522
   160547     162066       1519     160594     160547     165069    3288334336 3214526003         79       4522
   Inst_Min   Inst_Max   Inst_jitter last_Exec  Abs_min    Abs_max      tmp       Interval     Sample No
   160547     162212       1665     160584     160547     165069    1140850688 3214563875         80       4522
   160548     162285       1737     160586     160547     165069    3288334336 3214517959         81       4522
   160548     161531        983     160563     160547     165069    1140850688 3214518252         82       4522
   160547     162174       1627     160590     160547     165069    3288334336 3214531594         83       4522
   160547     161101        554     160577     160547     165069    1140850688 3214528979         84       4522
   160548     161131        583     160606     160547     165069    3288334336 3214514836         85       4522
   160549     161122        573     160592     160547     165069    1140850688 3214549460         86       4522
   160547     161109        562     160600     160547     165069    3288334336 3214505374         87       4522
   160547     161707       1160     160580     160547     165069    1140850688 3214535682         88       4522
   160547     161797       1250     160559     160547     165069    3288334336 3214538587         89       4522
   160547     161940       1393     160598     160547     165069    1140850688 3214527418         90       4522
   160547     161101        554     160598     160547     165069    3288334336 3214499605         91       4522
   160548     161125        577     160594     160547     165069    1140850688 3214547942         92       4522
   160547     162373       1826     160569     160547     165069    3288334336 3214524029         93       4522
   160547     162411       1864     160573     160547     165069    1140850688 3214511478         94       4522
   160547     161391        844     160557     160547     165069    3288334336 3214548809         95       4522
   160547     162281       1734     160558     160547     165069    1140850688 3214583716         96       4522
   160548     161134        586     160584     160547     165069    3288334336 3214536667         97       4522
   160547     164951       4404     160563     160547     165069    1140850688 3214516869         98       4522
   160547     161163        616     160600     160547     165069    3288334336 3214507206         99       4522
   160547     161166        619     160584     160547     165069    1140850688 3214509890        100       4522
   160548     161789       1241     160598     160547     165069    3288334336 3214538248        101       4522
   160547     162068       1521     160602     160547     165069    1140850688 3214501736        102       4522
   160548     161537        989     160606     160547     165069    3288334336 3214479851        103       4522
   160547     163492       2945     160571     160547     165069    1140850688 3214534229        104       4522
   160547     161722       1175     160580     160547     165069    3288334336 3214533470        105       4522
   160548     163118       2570     160555     160547     165069    1140850688 3214509914        106       4522
   160547     161465        918     160560     160547     165069    3288334336 3214554477        107       4522
   160547     161526        979     160606     160547     165069    1140850688 3214538842        108       4522
   160547     162723       2176     160556     160547     165069    3288334336 3214527778        109       4522
   160548     162411       1863     160600     160547     165069    1140850688 3214527170        110       4522
   160547     161326        779     160560     160547     165069    3288334336 3214528887        111       4522
   160547     162256       1709     160556     160547     165069    1140850688 3214551492        112       4522
   160548     161691       1143     160581     160547     165069    3288334336 3214511404        113       4522
   160548     161506        958     160578     160547     165069    1140850688 3214526723        114       4522
   160547     161737       1190     160580     160547     165069    3288334336 3214524835        115       4522
   160547     162318       1771     160588     160547     165069    1140850688 3214487335        116       4522
   160549     162340       1791     160555     160547     165069    3288334336 3214542565        117       4522
   160547     162200       1653     160608     160547     165069    1140850688 3214527323        118       4522
   160547     161645       1098     160555     160547     165069    3288334336 3214518498        119       4522
   Inst_Min   Inst_Max   Inst_jitter last_Exec  Abs_min    Abs_max      tmp       Interval     Sample No
   160548     161800       1252     160581     160547     165069    1140850688 3214509533        120       4522
   160547     161517        970     160581     160547     165069    3288334336 3214525581        121       4522
   160547     162644       2097     160552     160547     165069    1140850688 3214504862        122       4522
   160548     162527       1979     160596     160547     165069    3288334336 3214513609        123       4522
   160547     161399        852     160564     160547     165069    1140850688 3214526528        124       4522
   160547     161682       1135     160584     160547     165069    3288334336 3214556054        125       4522
   160548     161526        978     160581     160547     165069    1140850688 3214527651        126       4522
   160547     162248       1701     160608     160547     165069    3288334336 3214508968        127       4522
   160548     161843       1295     160580     160547     165069    1140850688 3214543081        128       4522
   160547     161997       1450     160559     160547     165069    3288334336 3214540805        129       4522
   160549     161139        590     160558     160547     165069    1140850688 3214496562        130       4522
   160548     161490        942     160594     160547     165069    3288334336 3214531954        131       4522
   160548     162131       1583     160577     160547     165069    1140850688 3214531735        132       4522
   160548     162509       1961     160574     160547     165069    3288334336 3214530014        133       4522
   160547     162398       1851     160586     160547     165069    1140850688 3214529600        134       4522
   160547     161505        958     160558     160547     165069    3288334336 3214548183        135       4522
   160547     161425        878     160568     160547     165069    1140850688 3214578516        136       4522
   160547     163305       2758     160608     160547     165069    3288334336 3214509344        137       4522
   160547     161160        613     160602     160547     165069    1140850688 3214488353        138       4522
   160547     161598       1051     160566     160547     165069    3288334336 3214535031        139       4522
   160547     161124        577     160570     160547     165069    1140850688 3214539796        140       4522
   160547     162460       1913     160594     160547     165069    3288334336 3214529212        141       4522
   160547     161449        902     160584     160547     165069    1140850688 3214514727        142       4522
   160548     161368        820     160602     160547     165069    3288334336 3214540973        143       4522
   160547     161172        625     160569     160547     165069    1140850688 3214518987        144       4522
   160547     162587       2040     160586     160547     165069    3288334336 3214522633        145       4522
   160547     162033       1486     160578     160547     165069    1140850688 3214522588        146       4522
   160547     163917       3370     160574     160547     165069    3288334336 3214520165        147       4522
   160547     161415        868     160558     160547     165069    1140850688 3214543910        148       4522
   160548     162465       1917     160593     160547     165069    3288334336 3214550611        149       4522
   160549     161144        595     160604     160547     165069    1140850688 3214547741        150       4522
   160548     162210       1662     160557     160547     165069    3288334336 3214525650        151       4522
   160548     162552       2004     160567     160547     165069    1140850688 3214503614        152       4522
   160547     161578       1031     160574     160547     165069    3288334336 3214571750        153       4522
   160548     162529       1981     160592     160547     165069    1140850688 3214522961        154       4522
   160547     161486        939     160592     160547     165069    3288334336 3214540246        155       4522
   160548     162037       1489     160565     160547     165069    1140850688 3214527079        156       4522
   160548     161212        664     160604     160547     165069    3288334336 3214544454        157       4522
   160548     161403        855     160561     160547     165069    1140850688 3214528247        158       4522
   160547     162352       1805     160588     160547     165069    3288334336 3214533400        159       4522
   Inst_Min   Inst_Max   Inst_jitter last_Exec  Abs_min    Abs_max      tmp       Interval     Sample No
   160547     162671       2124     160550     160547     165069    1140850688 3214511900        160       4522
   160547     161695       1148     160563     160547     165069    3288334336 3214558463        161       4522
   160547     161932       1385     160554     160547     165069    1140850688 3214491529        162       4522
   160547     162026       1479     160604     160547     165069    3288334336 3214519518        163       4522
   160547     163011       2464     160579     160547     165069    1140850688 3214553359        164       4522
   160547     161119        572     160608     160547     165069    3288334336 3214504545        165       4522
   160547     161444        897     160580     160547     165069    1140850688 3214548467        166       4522
   160548     162674       2126     160598     160547     165069    3288334336 3214514730        167       4522
   160547     162995       2448     160582     160547     165069    1140850688 3214537054        168       4522
   160548     162415       1867     160582     160547     165069    3288334336 3214524332        169       4522
   160547     162662       2115     160604     160547     165069    1140850688 3214554852        170       4522
   160547     162050       1503     160567     160547     165069    3288334336 3214504871        171       4522
   160547     161103        556     160608     160547     165069    1140850688 3214538849        172       4522
   160547     162358       1811     160551     160547     165069    3288334336 3214527248        173       4522
   160547     161411        864     160602     160547     165069    1140850688 3214518234        174       4522
   160547     161286        739     160571     160547     165069    3288334336 3214518875        175       4522
   160547     161620       1073     160606     160547     165069    1140850688 3214535921        176       4522
   160547     162381       1834     160582     160547     165069    3288334336 3214506713        177       4522
   160548     162359       1811     160584     160547     165069    1140850688 3214570455        178       4522
   160547     161545        998     160606     160547     165069    3288334336 3214555529        179       4522
   160548     161312        764     160555     160547     165069    1140850688 3214511377        180       4522
   160547     161342        795     160605     160547     165069    3288334336 3214533875        181       4522
   160547     161726       1179     160577     160547     165069    1140850688 3214543972        182       4522
   160548     162255       1707     160555     160547     165069    3288334336 3214543973        183       4522
   160548     162044       1496     160568     160547     165069    1140850688 3214502041        184       4522
   160548     161592       1044     160586     160547     165069    3288334336 3214530498        185       4522
   160547     162175       1628     160596     160547     165069    1140850688 3214541009        186       4522
   160547     162443       1896     160583     160547     165069    3288334336 3214558199        187       4522
   160547     164538       3991     160583     160547     165069    1140850688 3214521554        188       4522
   160548     161516        968     160560     160547     165069    3288334336 3214518328        189       4522
   160547     161458        911     160610     160547     165069    1140850688 3214512037        190       4522
   160548     161904       1356     160597     160547     165069    3288334336 3214496095        191       4522
   160548     162602       2054     160559     160547     165069    1140850688 3214522801        192       4522
   160547     162283       1736     160596     160547     165069    3288334336 3214527769        193       4522
   160547     161508        961     160580     160547     165069    1140850688 3214540086        194       4522
   160548     161523        975     160578     160547     165069    3288334336 3214523302        195       4522
   160548     161078        530     160588     160547     165069    1140850688 3214565283        196       4522
   160547     162656       2109     160606     160547     165069    3288334336 3214555008        197       4522
   160547     161399        852     160555     160547     165069    1140850688 3214521683        198       4522
   160548     161541        993     160550     160547     165069    3288334336 3214486334        199       4522
   Inst_Min   Inst_Max   Inst_jitter last_Exec  Abs_min    Abs_max      tmp       Interval     Sample No
   160547     162031       1484     160608     160547     165069    1140850688 3214523612        200       4522

Karbon 700 Core i7-9700TE - Jitter

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Attention

This benchmark utilizes CAT when present.

Linux Jitter testing program version 1.9
The pragram will execute a dummy function 80000 times
Display is updated every 20000 displayUpdate intervals
Thread affinity will be set to core_id:3
Timings are in CPU Core cycles
Inst_Min:    Minimum Excution time during the display update interval(default is ~1 second)
Inst_Max:    Maximum Excution time during the display update interval(default is ~1 second)
Inst_jitter: Jitter in the Excution time during rhe display update interval. This is the value of interest
last_Exec:   The Excution time of last iteration just before the display update
Abs_Min:     Absolute Minimum Excution time since the program started or statistics were reset
Abs_Max:     Absolute Maximum Excution time since the program started or statistics were reset
tmp:         Cumulative value calcualted by the dummy function
Interval:    Time interval between the display updates in Core Cycles
Sample No:   Sample number

   Inst_Min   Inst_Max   Inst_jitter last_Exec  Abs_min    Abs_max      tmp       Interval     Sample No
   84889      85141        252      84940      84889      85141    3366191104 1699526181          1        252
   84889      85224        335      84959      84889      85224      19136512 1699536075          2        335
   84883      85510        627      84934      84883      85510     967049216 1699531859          3        627
   84884      85337        453      84892      84883      85510    1914961920 1699530910          4        627
   84880      85318        438      84946      84880      85510    2862874624 1699336670          5        627
   84879      85123        244      84912      84879      85510    3810787328 1699336308          6        627
   84879      85076        197      84894      84879      85510     463732736 1699336613          7        627
   84889      85182        293      84898      84879      85510    1411645440 1699531115          8        627
   84879      85227        348      84916      84879      85510    2359558144 1699335817          9        627
   84879      85324        445      84944      84879      85510    3307470848 1699335756         10        627
   84882      85143        261      84951      84879      85510    4255383552 1699531896         11        627
   84884      85285        401      84904      84879      85510     908328960 1699533081         12        627
   84882      85157        275      84898      84879      85510    1856241664 1699531662         13        627
   84879      85362        483      84925      84879      85510    2804154368 1699336857         14        627
   84883      85194        311      84894      84879      85510    3752067072 1699530312         15        627
   84879      85292        413      84944      84879      85510     405012480 1699336854         16        627
   84879      85071        192      84910      84879      85510    1352925184 1699336535         17        627
   84880      85407        527      84895      84879      85510    2300837888 1699337521         18        627
   84882      85208        326      84896      84879      85510    3248750592 1699530882         19        627
   84879      85375        496      84922      84879      85510    4196663296 1699336520         20        627
   84879      85249        370      84941      84879      85510     849608704 1699336126         21        627
   84879      85236        357      84882      84879      85510    1797521408 1699336552         22        627
   84879      85080        201      84943      84879      85510    2745434112 1699336855         23        627
   84879      85117        238      84914      84879      85510    3693346816 1699336692         24        627
   84879      85373        494      84890      84879      85510     346292224 1699336377         25        627
   84879      85123        244      84951      84879      85510    1294204928 1699337333         26        627
   84882      85228        346      84925      84879      85510    2242117632 1699530805         27        627
   84882      85200        318      84892      84879      85510    3190030336 1699529675         28        627
   84879      85380        501      84935      84879      85510    4137943040 1699335858         29        627
   84879      85190        311      84931      84879      85510     790888448 1699335598         30        627
   84883      85265        382      84957      84879      85510    1738801152 1699532286         31        627
   84879      85206        327      84900      84879      85510    2686713856 1699336026         32        627
   84879      85326        447      84900      84879      85510    3634626560 1699336763         33        627
   84879      85125        246      84948      84879      85510     287571968 1699337623         34        627
   84879      85212        333      84884      84879      85510    1235484672 1699336766         35        627
   84879      85123        244      84934      84879      85510    2183397376 1699335940         36        627
   84883      85230        347      84894      84879      85510    3131310080 1699530678         37        627
   84879      85136        257      84920      84879      85510    4079222784 1699497776         38        627
   84879      85212        333      84944      84879      85510     732168192 1699336688         39        627
   Inst_Min   Inst_Max   Inst_jitter last_Exec  Abs_min    Abs_max      tmp       Interval     Sample No
   84883      85394        511      84949      84879      85510    1680080896 1699532111         40        627
   84885      85313        428      84894      84879      85510    2627993600 1699529689         41        627
   84884      85281        397      84908      84879      85510    3575906304 1699530789         42        627
   84889      85160        271      84955      84879      85510     228851712 1699531816         43        627
   84883      85325        442      84946      84879      85510    1176764416 1699530600         44        627
   84888      85141        253      84896      84879      85510    2124677120 1699531312         45        627
   84881      85316        435      84911      84879      85510    3072589824 1699530221         46        627
   84889      85141        252      84960      84879      85510    4020502528 1699530139         47        627
   84882      85196        314      84935      84879      85510     673447936 1699530562         48        627
   84889      85144        255      84890      84879      85510    1621360640 1699531220         49        627
   84884      85285        401      84912      84879      85510    2569273344 1699532291         50        627
   84884      85133        249      84959      84879      85510    3517186048 1699530373         51        627
   84882      85079        197      84930      84879      85510     170131456 1699529967         52        627
   84882      85080        198      84892      84879      85510    1118044160 1699529595         53        627
   84886      85362        476      84928      84879      85510    2065956864 1699530906         54        627
   84880      85056        176      84958      84879      85510    3013869568 1699529890         55        627
   84883      85374        491      84922      84879      85510    3961782272 1699532236         56        627
   84887      85228        341      84892      84879      85510     614727680 1699530487         57        627
   84882      85392        510      84936      84879      85510    1562640384 1699530466         58        627
   84887      85109        222      84959      84879      85510    2510553088 1699529670         59        627
   84881      85127        246      84902      84879      85510    3458465792 1699529266         60        627
   84884      85338        454      84900      84879      85510     111411200 1699530653         61        627
   84884      85131        247      84950      84879      85510    1059323904 1699531254         62        627
   84882      85275        393      84952      84879      85510    2007236608 1699530470         63        627
   84882      85140        258      84896      84879      85510    2955149312 1699529228         64        627
   84882      85306        424      84910      84879      85510    3903062016 1699529777         65        627
   84889      85187        298      84957      84879      85510     556007424 1699531409         66        627
   84882      85129        247      84944      84879      85510    1503920128 1699531745         67        627
   84882      85054        172      84896      84879      85510    2451832832 1699530878         68        627
   84882      85164        282      84908      84879      85510    3399745536 1699530910         69        627
   84882      85141        259      84959      84879      85510      52690944 1699531107         70        627
   84883      85391        508      84942      84879      85510    1000603648 1699531599         71        627
   84890      85052        162      84891      84879      85510    1948516352 1699528968         72        627
   84882      85334        452      84918      84879      85510    2896429056 1699530602         73        627
   84882      85133        251      84961      84879      85510    3844341760 1699530258         74        627
   84882      85258        376      84922      84879      85510     497287168 1699530371         75        627
   84889      85188        299      84890      84879      85510    1445199872 1699530821         76        627
   84884      85265        381      84930      84879      85510    2393112576 1699531137         77        627
   84884      85098        214      84959      84879      85510    3341025280 1699530377         78        627
   84883      85214        331      84913      84879      85510    4288937984 1699529749         79        627
   Inst_Min   Inst_Max   Inst_jitter last_Exec  Abs_min    Abs_max      tmp       Interval     Sample No
   84889      85385        496      84894      84879      85510     941883392 1699531060         80        627
   84883      85139        256      84943      84879      85510    1889796096 1699530130         81        627
   84882      85350        468      84957      84879      85510    2837708800 1699531621         82        627
   84882      85212        330      84907      84879      85510    3785621504 1699530329         83        627
   84884      85308        424      84898      84879      85510     438566912 1699529878         84        627
   84886      85085        199      84951      84879      85510    1386479616 1699530807         85        627
   84882      85204        322      84949      84879      85510    2334392320 1699530381         86        627
   84884      85062        178      84898      84879      85510    3282305024 1699530221         87        627
   84883      85190        307      84904      84879      85510    4230217728 1699530867         88        627
   84886      85374        488      84956      84879      85510     883163136 1699530168         89        627
   84882      85385        503      84942      84879      85510    1831075840 1699530367         90        627
   84882      85366        484      84893      84879      85510    2778988544 1699530304         91        627
   84882      85168        286      84916      84879      85510    3726901248 1699529903         92        627
   84882      85123        241      84959      84879      85510     379846656 1699530975         93        627
   84882      85117        235      84933      84879      85510    1327759360 1699531559         94        627
   84889      85125        236      84893      84879      85510    2275672064 1699528992         95        627
   84883      85131        248      84924      84879      85510    3223584768 1699532054         96        627
   84889      85215        326      84959      84879      85510    4171497472 1699531117         97        627
   84882      85362        480      84933      84879      85510     824442880 1699532246         98        627
   84883      85358        475      84890      84879      85510    1772355584 1699529929         99        627
   84883      85174        291      84927      84879      85510    2720268288 1699530738        100        627
   84881      85161        280      84959      84879      85510    3668180992 1699530048        101        627
   84884      85275        391      84915      84879      85510     321126400 1699530175        102        627
   84882      85133        251      84894      84879      85510    1269039104 1699529878        103        627
   84882      85139        257      84942      84879      85510    2216951808 1699530695        104        627
   84880      85399        519      84959      84879      85510    3164864512 1699531948        105        627
   84884      85222        338      84912      84879      85510    4112777216 1699531445        106        627
   84884      85121        237      84894      84879      85510     765722624 1699530554        107        627
   84882      85252        370      84941      84879      85510    1713635328 1699531401        108        627
   84889      85224        335      84956      84879      85510    2661548032 1699530747        109        627
   84882      85376        494      84906      84879      85510    3609460736 1699529944        110        627
   84882      85377        495      84895      84879      85510     262406144 1699530954        111        627
   84885      85086        201      84951      84879      85510    1210318848 1699530493        112        627
   84883      85052        169      84954      84879      85510    2158231552 1699531080        113        627
   84882      85370        488      84904      84879      85510    3106144256 1699531517        114        627
   84882      85477        595      84898      84879      85510    4054056960 1699531269        115        627
   84887      85194        307      84949      84879      85510     707002368 1699530602        116        627
   84881      85348        467      84951      84879      85510    1654915072 1699531135        117        627
   84885      85141        256      84900      84879      85510    2602827776 1699530776        118        627
   84882      85125        243      84902      84879      85510    3550740480 1699531419        119        627
   Inst_Min   Inst_Max   Inst_jitter last_Exec  Abs_min    Abs_max      tmp       Interval     Sample No
   84889      85159        270      84949      84879      85510     203685888 1699532317        120        627
   84882      85228        346      84951      84879      85510    1151598592 1699529404        121        627
   84882      85388        506      84902      84879      85510    2099511296 1699531984        122        627
   84882      85176        294      84900      84879      85510    3047424000 1699531310        123        627
   84882      85339        457      84951      84879      85510    3995336704 1699531056        124        627
   84882      85141        259      84945      84879      85510     648282112 1699529787        125        627
   84883      85142        259      84896      84879      85510    1596194816 1699530860        126        627
   84883      85161        278      84908      84879      85510    2544107520 1699529349        127        627
   84884      85342        458      84959      84879      85510    3492020224 1699531425        128        627
   84885      85259        374      84938      84879      85510     144965632 1699530385        129        627
   84888      85106        218      84894      84879      85510    1092878336 1699531652        130        627
   84884      85341        457      84906      84879      85510    2040791040 1699532159        131        627
   84886      85097        211      84955      84879      85510    2988703744 1699531417        132        627
   84882      85482        600      84944      84879      85510    3936616448 1699530656        133        627
   84886      85223        337      84894      84879      85510     589561856 1699529429        134        627
   84886      85074        188      84922      84879      85510    1537474560 1699529596        135        627
   84883      85196        313      84959      84879      85510    2485387264 1699532123        136        627
   84885      85079        194      84929      84879      85510    3433299968 1699530306        137        627
   84884      85119        235      84890      84879      85510      86245376 1699531745        138        627
   84882      85162        280      84916      84879      85510    1034158080 1699531480        139        627
   84889      85400        511      84959      84879      85510    1982070784 1699531569        140        627
   84882      85135        253      84933      84879      85510    2929983488 1699530592        141        627
   84889      85192        303      84892      84879      85510    3877896192 1699530480        142        627
   84884      85448        564      84920      84879      85510     530841600 1699531553        143        627
   84889      85401        512      84959      84879      85510    1478754304 1699530857        144        627
   84880      85131        251      84928      84879      85510    2426667008 1699530172        145        627
   84889      85316        427      84891      84879      85510    3374579712 1699531196        146        627
   84883      85099        216      84928      84879      85510      27525120 1699530813        147        627
   84882      85075        193      84957      84879      85510     975437824 1699529656        148        627
   84884      85054        170      84915      84879      85510    1923350528 1699530436        149        627
   84889      85387        498      84892      84879      85510    2871263232 1699530379        150        627
   84884      85188        304      84940      84879      85510    3819175936 1699531564        151        627
   84884      85169        285      84955      84879      85510     472121344 1699530329        152        627
   84884      85138        254      84904      84879      85510    1420034048 1699530109        153        627
   84882      85269        387      84896      84879      85510    2367946752 1699530136        154        627
   84880      85074        194      84949      84879      85510    3315859456 1699530527        155        627
   84882      85443        561      84948      84879      85510    4263772160 1699530468        156        627
   84886      85070        184      84900      84879      85510     916717568 1699530900        157        627
   84884      85365        481      84904      84879      85510    1864630272 1699531393        158        627
   84884      85133        249      84957      84879      85510    2812542976 1699528741        159        627
   Inst_Min   Inst_Max   Inst_jitter last_Exec  Abs_min    Abs_max      tmp       Interval     Sample No
   84883      85405        522      84942      84879      85510    3760455680 1699531437        160        627
   84888      85135        247      84895      84879      85510     413401088 1699530464        161        627
   84882      85217        335      84908      84879      85510    1361313792 1699532115        162        627
   84882      85141        259      84957      84879      85510    2309226496 1699530618        163        627
   84884      85166        282      84943      84879      85510    3257139200 1699531184        164        627
   84883      85336        453      84896      84879      85510    4205051904 1699531317        165        627
   84882      85587        705      84907      84879      85587     857997312 1699531669        166        705
   84886      85141        255      84959      84879      85587    1805910016 1699530079        167        705
   84882      85220        338      84938      84879      85587    2753822720 1699530360        168        705
   84889      85224        335      84892      84879      85587    3701735424 1699530450        169        705
   84882      85117        235      84916      84879      85587     354680832 1699531926        170        705
   84889      85074        185      84959      84879      85587    1302593536 1699530164        171        705
   84881      85190        309      84932      84879      85587    2250506240 1699531496        172        705
   84889      85194        305      84892      84879      85587    3198418944 1699531006        173        705
   84886      85142        256      84920      84879      85587    4146331648 1699530567        174        705
   84889      85133        244      84959      84879      85587     799277056 1699531164        175        705
   84882      85123        241      84924      84879      85587    1747189760 1699529963        176        705
   84889      85228        339      84892      84879      85587    2695102464 1699529899        177        705
   84884      85137        253      84934      84879      85587    3643015168 1699530928        178        705
   84884      85134        250      84961      84879      85587     295960576 1699530353        179        705
   84882      85157        275      84908      84879      85587    1243873280 1699529876        180        705
   84889      85374        485      84896      84879      85587    2191785984 1699531231        181        705
   84884      85137        253      84946      84879      85587    3139698688 1699529973        182        705
   84889      85318        429      84957      84879      85587    4087611392 1699531768        183        705
   84884      85133        249      84904      84879      85587     740556800 1699529860        184        705
   84884      85225        341      84898      84879      85587    1688469504 1699531299        185        705
   84884      85135        251      84948      84879      85587    2636382208 1699530904        186        705
   84885      85370        485      84953      84879      85587    3584294912 1699530384        187        705
   84886      85182        296      84900      84879      85587     237240320 1699530326        188        705
   84884      85127        243      84904      84879      85587    1185153024 1699530711        189        705
   84886      85251        365      84953      84879      85587    2133065728 1699531456        190        705
   84886      85052        166      84948      84879      85587    3080978432 1699530709        191        705
   84882      85350        468      84896      84879      85587    4028891136 1699531314        192        705
   84882      85403        521      84905      84879      85587     681836544 1699530059        193        705
   84889      85216        327      84953      84879      85587    1629749248 1699532227        194        705
   84881      85395        514      84953      84879      85587    2577661952 1699533744        195        705
   84886      85139        253      84904      84879      85587    3525574656 1699530547        196        705
   84882      85265        383      84900      84879      85587     178520064 1699530809        197        705
   84886      85129        243      84949      84879      85587    1126432768 1699531247        198        705
   84882      85498        616      84953      84879      85587    2074345472 1699532049        199        705
   Inst_Min   Inst_Max   Inst_jitter last_Exec  Abs_min    Abs_max      tmp       Interval     Sample No
   84882      85388        506      84902      84879      85587    3022258176 1699531591        200        705

TGL-RVP Core i7-1185GRE - Jitter

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Attention

This benchmark utilizes Cache Allocation Technology when present.

Linux Jitter testing program version 1.9
The pragram will execute a dummy function 80000 times
Display is updated every 20000 displayUpdate intervals
Thread affinity will be set to core_id:3
Timings are in CPU Core cycles
Inst_Min:    Minimum Excution time during the display update interval(default is ~1 second)
Inst_Max:    Maximum Excution time during the display update interval(default is ~1 second)
Inst_jitter: Jitter in the Excution time during rhe display update interval. This is the value of interest
last_Exec:   The Excution time of last iteration just before the display update
Abs_Min:     Absolute Minimum Excution time since the program started or statistics were reset
Abs_Max:     Absolute Maximum Excution time since the program started or statistics were reset
tmp:         Cumulative value calcualted by the dummy function
Interval:    Time interval between the display updates in Core Cycles
Sample No:   Sample number

   Inst_Min   Inst_Max   Inst_jitter last_Exec  Abs_min    Abs_max      tmp       Interval     Sample No
   160547     166610       6063     160572     160547     166610    3657433088 3213929741          1       6063
   160548     173333      12785     160566     160547     173333     436207616 3214564995          2      12785
   160548     173363      12815     160552     160547     173363    1509949440 3214561195          3      12815
   160547     174010      13463     160553     160547     174010    2583691264 3214562531          4      13463
   160547     170219       9672     160846     160547     174010    3657433088 3214542933          5      13463
   160548     172643      12095     160602     160547     174010     436207616 3214738461          6      13463
   160548     172846      12298     160606     160547     174010    1509949440 3214732307          7      13463
   160547     173255      12708     160567     160547     174010    2583691264 3214980555          8      13463
   160548     171497      10949     160561     160547     174010    3657433088 3215074697          9      13463
   160548     172973      12425     160574     160547     174010     436207616 3214996328         10      13463
   160549     173268      12719     161086     160547     174010    1509949440 3215057416         11      13463
   160547     175463      14916     160577     160547     175463    2583691264 3215046371         12      14916
   160548     170810      10262     160562     160547     175463    3657433088 3215036584         13      14916
   160547     166535       5988     160945     160547     175463     436207616 3215045079         14      14916
   160547     162314       1767     160586     160547     175463    1509949440 3215021689         15      14916
   160547     170190       9643     160572     160547     175463    2583691264 3215017289         16      14916
   160548     162385       1837     160551     160547     175463    3657433088 3215021281         17      14916
   160548     169234       8686     160553     160547     175463     436207616 3215006316         18      14916
   160548     169017       8469     160598     160547     175463    1509949440 3214980142         19      14916
   160548     162265       1717     160584     160547     175463    2583691264 3215014935         20      14916
   160548     175169      14621     160564     160547     175463    3657433088 3215020014         21      14916
   160549     162609       2060     160608     160547     175463     436207616 3214976206         22      14916
   160548     162129       1581     160593     160547     175463    1509949440 3214993482         23      14916
   160549     162028       1479     160577     160547     175463    2583691264 3214995186         24      14916
   160547     162502       1955     160606     160547     175463    3657433088 3215028387         25      14916
   160548     162033       1485     160608     160547     175463     436207616 3215010680         26      14916
   160547     162198       1651     160592     160547     175463    1509949440 3214995334         27      14916
   160547     162221       1674     160829     160547     175463    2583691264 3214965856         28      14916
   160548     162133       1585     160579     160547     175463    3657433088 3214998039         29      14916
   160549     172200      11651     160606     160547     175463     436207616 3214981627         30      14916
   160548     162393       1845     160588     160547     175463    1509949440 3215026466         31      14916
   160547     170956      10409     160567     160547     175463    2583691264 3215022883         32      14916
   160547     162160       1613     160750     160547     175463    3657433088 3215036979         33      14916
   160549     162047       1498     160553     160547     175463     436207616 3214993957         34      14916
   160548     162113       1565     160554     160547     175463    1509949440 3215008730         35      14916
   160548     161926       1378     160598     160547     175463    2583691264 3214970801         36      14916
   160548     171515      10967     160821     160547     175463    3657433088 3215034515         37      14916
   160548     168259       7711     160566     160547     175463     436207616 3215000144         38      14916
   160547     163356       2809     160568     160547     175463    1509949440 3215036800         39      14916
   Inst_Min   Inst_Max   Inst_jitter last_Exec  Abs_min    Abs_max      tmp       Interval     Sample No
   160549     175452      14903     160580     160547     175463    2583691264 3215014359         40      14916
   160547     166781       6234     160607     160547     175463    3657433088 3215027091         41      14916
   160547     173676      13129     160607     160547     175463     436207616 3215098266         42      14916
   160549     173166      12617     160590     160547     175463    1509949440 3215023013         43      14916
   160548     175888      15340     160567     160547     175888    2583691264 3215048226         44      15340
   160547     169991       9444     160606     160547     175888    3657433088 3215033789         45      15340
   160547     162170       1623     160582     160547     175888     436207616 3214992317         46      15340
   160548     170597      10049     160592     160547     175888    1509949440 3215013178         47      15340
   160548     169712       9164     160584     160547     175888    2583691264 3215002796         48      15340
   160548     171484      10936     160569     160547     175888    3657433088 3215054770         49      15340
   160547     173219      12672     160606     160547     175888     436207616 3215070693         50      15340
   160547     171023      10476     160555     160547     175888    1509949440 3215040928         51      15340
   160548     163871       3323     160602     160547     175888    2583691264 3214978684         52      15340
   160548     162040       1492     160582     160547     175888    3657433088 3214979321         53      15340
   160547     162333       1786     160596     160547     175888     436207616 3215037653         54      15340
   160547     170559      10012     160580     160547     175888    1509949440 3215019771         55      15340
   160549     175762      15213     160598     160547     175888    2583691264 3215082776         56      15340
   160547     170864      10317     160572     160547     175888    3657433088 3215059043         57      15340
   160548     162546       1998     160581     160547     175888     436207616 3215013999         58      15340
   160547     162332       1785     160557     160547     175888    1509949440 3214977226         59      15340
   160547     162342       1795     160598     160547     175888    2583691264 3214980552         60      15340
   160547     162332       1785     160850     160547     175888    3657433088 3214982697         61      15340
   160547     162338       1791     160559     160547     175888     436207616 3214987719         62      15340
   160547     162395       1848     160563     160547     175888    1509949440 3215010228         63      15340
   160547     171666      11119     160921     160547     175888    2583691264 3215013759         64      15340
   160547     170704      10157     160567     160547     175888    3657433088 3215063481         65      15340
   160547     172623      12076     160606     160547     175888     436207616 3215069822         66      15340
   160548     162293       1745     160572     160547     175888    1509949440 3214975639         67      15340
   160548     163762       3214     160551     160547     175888    2583691264 3214991515         68      15340
   160547     173156      12609     160872     160547     175888    3657433088 3215024115         69      15340
   160547     170581      10034     160600     160547     175888     436207616 3215044024         70      15340
   160547     162466       1919     160608     160547     175888    1509949440 3214997084         71      15340
   160547     166073       5526     160608     160547     175888    2583691264 3215006536         72      15340
   160547     162089       1542     160576     160547     175888    3657433088 3214984522         73      15340
   160548     162381       1833     160817     160547     175888     436207616 3214979979         74      15340
   160548     162191       1643     160559     160547     175888    1509949440 3215026505         75      15340
   160547     162277       1730     160572     160547     175888    2583691264 3214982004         76      15340
   160548     162466       1918     160554     160547     175888    3657433088 3215016508         77      15340
   160547     162356       1809     160598     160547     175888     436207616 3214961330         78      15340
   160549     162107       1558     160581     160547     175888    1509949440 3215080484         79      15340
   Inst_Min   Inst_Max   Inst_jitter last_Exec  Abs_min    Abs_max      tmp       Interval     Sample No
   160547     171933      11386     160829     160547     175888    2583691264 3215004443         80      15340
   160548     162133       1585     160558     160547     175888    3657433088 3214997863         81      15340
   160548     162305       1757     160596     160547     175888     436207616 3214969269         82      15340
   160548     162490       1942     160583     160547     175888    1509949440 3214972772         83      15340
   160548     163459       2911     160560     160547     175888    2583691264 3215064109         84      15340
   160547     163472       2925     160598     160547     175888    3657433088 3214962840         85      15340
   160547     164664       4117     160577     160547     175888     436207616 3215042930         86      15340
   160547     169083       8536     160588     160547     175888    1509949440 3215053574         87      15340
   160548     162214       1666     160568     160547     175888    2583691264 3214993424         88      15340
   160548     172460      11912     160561     160547     175888    3657433088 3215073018         89      15340
   160548     164438       3890     160570     160547     175888     436207616 3215002535         90      15340
   160548     169344       8796     160590     160547     175888    1509949440 3215049267         91      15340
   160548     170316       9768     160914     160547     175888    2583691264 3215077860         92      15340
   160547     162759       2212     160573     160547     175888    3657433088 3215014042         93      15340
   160548     173077      12529     160890     160547     175888     436207616 3215024050         94      15340
   160547     165619       5072     160596     160547     175888    1509949440 3215028751         95      15340
   160548     170136       9588     160555     160547     175888    2583691264 3215035178         96      15340
   160548     170934      10386     160555     160547     175888    3657433088 3215020434         97      15340
   160548     169670       9122     160551     160547     175888     436207616 3215001255         98      15340
   160548     164840       4292     160566     160547     175888    1509949440 3214993203         99      15340
   160548     162129       1581     160553     160547     175888    2583691264 3215020768        100      15340
   160547     171646      11099     160562     160547     175888    3657433088 3215020337        101      15340
   160547     163499       2952     160554     160547     175888     436207616 3214998848        102      15340
   160547     165479       4932     160949     160547     175888    1509949440 3214990141        103      15340
   160547     174857      14310     160598     160547     175888    2583691264 3215076437        104      15340
   160547     175906      15359     160550     160547     175906    3657433088 3215042577        105      15359
   160547     173823      13276     160914     160547     175906     436207616 3215034713        106      15359
   160547     174735      14188     160598     160547     175906    1509949440 3215032982        107      15359
   160547     172306      11759     160560     160547     175906    2583691264 3215049200        108      15359
   160547     176137      15590     160577     160547     176137    3657433088 3215108891        109      15590
   160549     175039      14490     160557     160547     176137     436207616 3215080819        110      15590
   160549     170526       9977     160574     160547     176137    1509949440 3215019704        111      15590
   160549     164536       3987     160604     160547     176137    2583691264 3215025217        112      15590
   160547     170534       9987     160566     160547     176137    3657433088 3215043839        113      15590
   160548     168721       8173     160564     160547     176137     436207616 3215009141        114      15590
   160549     171457      10908     160868     160547     176137    1509949440 3215067685        115      15590
   160547     172481      11934     160602     160547     176137    2583691264 3215011923        116      15590
   160548     162366       1818     160555     160547     176137    3657433088 3215037907        117      15590
   160548     169103       8555     160554     160547     176137     436207616 3215007615        118      15590
   160547     162194       1647     160554     160547     176137    1509949440 3215018550        119      15590
   Inst_Min   Inst_Max   Inst_jitter last_Exec  Abs_min    Abs_max      tmp       Interval     Sample No
   160548     162512       1964     160557     160547     176137    2583691264 3215006486        120      15590
   160547     171780      11233     160552     160547     176137    3657433088 3215008578        121      15590
   160547     162251       1704     160576     160547     176137     436207616 3214985438        122      15590
   160547     162560       2013     160606     160547     176137    1509949440 3214985643        123      15590
   160548     163469       2921     160553     160547     176137    2583691264 3215050068        124      15590
   160548     162725       2177     160600     160547     176137    3657433088 3214970768        125      15590
   160548     162192       1644     160610     160547     176137     436207616 3214996171        126      15590
   160548     162266       1718     160602     160547     176137    1509949440 3215001949        127      15590
   160548     162401       1853     160574     160547     176137    2583691264 3214989666        128      15590
   160547     167983       7436     160587     160547     176137    3657433088 3215013328        129      15590
   160547     162356       1809     160815     160547     176137     436207616 3214986562        130      15590
   160548     171230      10682     160575     160547     176137    1509949440 3214984333        131      15590
   160548     162486       1938     160588     160547     176137    2583691264 3214999970        132      15590
   160548     162125       1577     160596     160547     176137    3657433088 3215003776        133      15590
   160547     162208       1661     160588     160547     176137     436207616 3215010595        134      15590
   160547     162455       1908     160608     160547     176137    1509949440 3214992294        135      15590
   160547     164196       3649     160602     160547     176137    2583691264 3214999979        136      15590
   160547     162465       1918     160827     160547     176137    3657433088 3215044853        137      15590
   160547     172572      12025     160568     160547     176137     436207616 3215036731        138      15590
   160547     174085      13538     160610     160547     176137    1509949440 3215034338        139      15590
   160547     166500       5953     160841     160547     176137    2583691264 3214986529        140      15590
   160547     162397       1850     160564     160547     176137    3657433088 3214996460        141      15590
   160547     162081       1534     160576     160547     176137     436207616 3214978021        142      15590
   160548     164081       3533     160570     160547     176137    1509949440 3215010587        143      15590
   160547     163327       2780     160606     160547     176137    2583691264 3214980736        144      15590
   160547     162085       1538     160886     160547     176137    3657433088 3215021956        145      15590
   160547     171369      10822     160571     160547     176137     436207616 3215050816        146      15590
   160547     171035      10488     160594     160547     176137    1509949440 3215024575        147      15590
   160547     164638       4091     160587     160547     176137    2583691264 3215002384        148      15590
   160547     174866      14319     160576     160547     176137    3657433088 3214999966        149      15590
   160548     172232      11684     160584     160547     176137     436207616 3215012846        150      15590
   160547     170765      10218     160608     160547     176137    1509949440 3215027212        151      15590
   160548     175585      15037     160557     160547     176137    2583691264 3215057098        152      15590
   160547     171680      11133     160564     160547     176137    3657433088 3215079234        153      15590
   160547     173982      13435     160586     160547     176137     436207616 3215080350        154      15590
   160547     169903       9356     160566     160547     176137    1509949440 3215018522        155      15590
   160548     175794      15246     160574     160547     176137    2583691264 3215040079        156      15590
   160548     175879      15331     160976     160547     176137    3657433088 3215062334        157      15590
   160547     164956       4409     160575     160547     176137     436207616 3215004823        158      15590
   160547     167619       7072     160576     160547     176137    1509949440 3215005313        159      15590
   Inst_Min   Inst_Max   Inst_jitter last_Exec  Abs_min    Abs_max      tmp       Interval     Sample No
   160548     162374       1826     160554     160547     176137    2583691264 3215033408        160      15590
   160547     162258       1711     160557     160547     176137    3657433088 3214994285        161      15590
   160547     170936      10389     160553     160547     176137     436207616 3215012899        162      15590
   160547     169513       8966     160748     160547     176137    1509949440 3215028283        163      15590
   160547     173950      13403     160604     160547     176137    2583691264 3215025919        164      15590
   160547     166945       6398     160571     160547     176137    3657433088 3214986949        165      15590
   160548     162329       1781     160863     160547     176137     436207616 3214981606        166      15590
   160547     162409       1862     160596     160547     176137    1509949440 3215049107        167      15590
   160547     170246       9699     160559     160547     176137    2583691264 3214984988        168      15590
   160548     166192       5644     160880     160547     176137    3657433088 3214986294        169      15590
   160549     162902       2353     160582     160547     176137     436207616 3214997500        170      15590
   160547     171108      10561     160563     160547     176137    1509949440 3215039884        171      15590
   160547     167696       7149     160582     160547     176137    2583691264 3215018627        172      15590
   160548     170663      10115     160584     160547     176137    3657433088 3215049654        173      15590
   160547     171727      11180     160596     160547     176137     436207616 3215000110        174      15590
   160548     168027       7479     160592     160547     176137    1509949440 3215009871        175      15590
   160547     165730       5183     160916     160547     176137    2583691264 3214999166        176      15590
   160547     162283       1736     160567     160547     176137    3657433088 3215032718        177      15590
   160549     170668      10119     160552     160547     176137     436207616 3215019467        178      15590
   160548     162366       1818     160568     160547     176137    1509949440 3215024325        179      15590
   160548     170012       9464     160588     160547     176137    2583691264 3215052742        180      15590
   160549     162190       1641     160725     160547     176137    3657433088 3215036139        181      15590
   160548     162613       2065     160608     160547     176137     436207616 3215047426        182      15590
   160547     170285       9738     160564     160547     176137    1509949440 3214978540        183      15590
   160548     162291       1743     160561     160547     176137    2583691264 3214984848        184      15590
   160548     162451       1903     160578     160547     176137    3657433088 3215037536        185      15590
   160548     170599      10051     160578     160547     176137     436207616 3215010727        186      15590
   160548     162271       1723     160587     160547     176137    1509949440 3215009751        187      15590
   160549     162386       1837     160586     160547     176137    2583691264 3215048028        188      15590
   160547     162310       1763     160560     160547     176137    3657433088 3215038074        189      15590
   160548     162398       1850     160862     160547     176137     436207616 3215036970        190      15590
   160547     162409       1862     160561     160547     176137    1509949440 3214981829        191      15590
   160548     162710       2162     160567     160547     176137    2583691264 3214983518        192      15590
   160547     162184       1637     160896     160547     176137    3657433088 3214989036        193      15590
   160547     165218       4671     160608     160547     176137     436207616 3214996674        194      15590
   160548     162135       1587     160606     160547     176137    1509949440 3215011885        195      15590
   160547     166489       5942     160598     160547     176137    2583691264 3215011469        196      15590
   160547     162634       2087     160913     160547     176137    3657433088 3215029048        197      15590
   160547     162407       1860     160576     160547     176137     436207616 3215002597        198      15590
   160548     162802       2254     160584     160547     176137    1509949440 3214959791        199      15590
   Inst_Min   Inst_Max   Inst_jitter last_Exec  Abs_min    Abs_max      tmp       Interval     Sample No
   160547     162223       1676     160553     160547     176137    2583691264 3214987618        200      15590

Caterpillar Results

See also

See section Caterpillar for more information on this benchmark.

Attention

This benchmark utilizes Cache Allocation Technology (CAT) when present.

The following configuration was used:

• Core affinity = 3

• Priority = -20 nice -n -20

• Noisy Neighbor stress-ng affinity = 0

• CAT used to assign 0x0f to COS0

• CAT used to assign 0xf0 to COS1

• SSH session (not using integrated GPU)

Vecow Core i7-8665UE - Caterpillar

Click to toggle results

Attention

This benchmark utilizes (CAT) when present.

Cache Allocation Technology (CAT)erpillar benchmark v1.1

The benchmark will execute an operation function 50000 times.
Samples are taken every 10000 test cycles.
A total of 200 samples will be measured.
Thread affinity will be set to core_id: 3

Timings are in CPU Core cycles

SampleMin:       Minimum execution time during the display update interval
SampleMax:       Maximum execution time during the display update interval
SmplJitter:      Jitter in the execution time during the display update interval
SessionMin:      Minimum execution time since the program started or statistics were reset
SessionMax:      Maximum execution time since the program started or statistics were reset
SessionJitter:   Jitter in the execution since the program started or statistics were reset
Sample:          Sample number

Priming cache...

SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   158801     299420       8430       158801     299420       8430          0
   158809     300595       8426       158801     300595       8428          1
   158804     300189       8266       158801     300595       8375          2
   158795     298628       8108       158795     300595       8309          3
   158791     298839       8304       158791     300595       8308          4
   158806     299437       8386       158791     300595       8322          5
   158799     300754       8499       158791     300754       8347          6
   158809     302152       8451       158791     302152       8361          7
   158799     299851       8314       158791     302152       8356          8
   158805     297041       8413       158791     302152       8362          9
   158806     298576       8494       158791     302152       8374         10
   158806     297966       8483       158791     302152       8383         11
   158807     298782       8566       158791     302152       8398         12
   158801     296282       8454       158791     302152       8403         13
   158805     296545       8472       158791     302152       8409         14
   158811     310574       8460       158791     310574       8412         15
   158788     295117       8601       158788     310574       8424         16
   158795     297049       8512       158788     310574       8429         17
   158805     296506       8678       158788     310574       8442         18
   158803     296557       8650       158788     310574       8452         19
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   158806     292718       8627       158788     310574       8461         20
   158801     298497       8680       158788     310574       8472         21
   158807     294500       8733       158788     310574       8484         22
   158806     297788       8686       158788     310574       8493         23
   158807     297267       8759       158788     310574       8505         24
   158805     296158       8733       158788     310574       8516         25
   158809     293623       8681       158788     310574       8523         26
   158808     296667       8711       158788     310574       8531         27
   158805     295531       8694       158788     310574       8537         28
   158805     294753       8629       158788     310574       8541         29
   158793     293067       8691       158788     310574       8547         30
   158808     297770       8604       158788     310574       8550         31
   158806     295858       8646       158788     310574       8553         32
   158805     293263       8535       158788     310574       8553         33
   158805     293450       8426       158788     310574       8550         34
   158805     292632       8626       158788     310574       8553         35
   158810     293162       8692       158788     310574       8557         36
   158827     293101       8627       158788     310574       8559         37
   158800     293761       8650       158788     310574       8562         38
   158833     293877       8558       158788     310574       8562         39
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   158856     291749       8533       158788     310574       8562         40
   158840     288648       8521       158788     310574       8561         41
   158826     292760       8639       158788     310574       8564         42
   158828     291563       8606       158788     310574       8565         43
   158819     290992       8549       158788     310574       8566         44
   158799     289769       8495       158788     310574       8565         45
   158826     290837       8589       158788     310574       8567         46
   158834     293096       8585       158788     310574       8569         47
   158844     290994       8681       158788     310574       8574         48
   158816     291296       8429       158788     310574       8573         49
   158838     291876       8544       158788     310574       8575         50
   158864     292609       8451       158788     310574       8575         51
   158852     289883       8483       158788     310574       8575         52
   158858     289711       8437       158788     310574       8575         53
   158799     289564       8426       158788     310574       8574         54
   158816     289761       8430       158788     310574       8574         55
   158812     288674       8421       158788     310574       8573         56
   158817     291097       8367       158788     310574       8572         57
   158810     288809       8466       158788     310574       8572         58
   158821     291227       8376       158788     310574       8571         59
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   158824     288769       8434       158788     310574       8570         60
   158858     287587       8397       158788     310574       8569         61
   158819     288859       8482       158788     310574       8570         62
   158830     284046       8395       158788     310574       8569         63
   158816     287862       8134       158788     310574       8564         64
   158858     286929       8464       158788     310574       8564         65
   158842     286561       8534       158788     310574       8565         66
   158797     286419       8358       158788     310574       8564         67
   158818     284813       8464       158788     310574       8564         68
   158805     287010       8344       158788     310574       8562         69
   158824     285136       8386       158788     310574       8561         70
   158815     279038       8251       158788     310574       8558         71
   158828     284860       8373       158788     310574       8557         72
   158811     285182       8220       158788     310574       8554         73
   158815     286040       8512       158788     310574       8555         74
   158814     284927       8569       158788     310574       8556         75
   158807     284169       8422       158788     310574       8556         76
   158808     285041       8413       158788     310574       8555         77
   158833     285166       8188       158788     310574       8552         78
   158866     281362       8442       158788     310574       8552         79
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   158838     283233       8445       158788     310574       8552         80
   158820     284403       8492       158788     310574       8552         81
   158837     283811       8501       158788     310574       8552         82
   158831     284131       8490       158788     310574       8553         83
   158829     284931       8513       158788     310574       8553         84
   158822     332923       8569       158788     332923       8555         85
   158820     282435       8522       158788     332923       8555         86
   158808     293411       8420       158788     332923       8555         87
   158852     282378       8403       158788     332923       8554         88
   158849     280068       8470       158788     332923       8554         89
   158802     280677       8443       158788     332923       8554         90
   158870     281933       8521       158788     332923       8554         91
   158848     281439       8414       158788     332923       8554         92
   158888     279453       8458       158788     332923       8554         93
   158841     280924       8455       158788     332923       8553         94
   158831     283502       8527       158788     332923       8554         95
   158836     280481       8472       158788     332923       8556         96
   158835     279987       8423       158788     332923       8558         97
   158822     280287       8242       158788     332923       8558         98
   158840     281467       8465       158788     332923       8560         99
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   158810     301711       8435       158788     332923       8562        100
   158856     278645       8398       158788     332923       8564        101
   158842     284390       8521       158788     332923       8567        102
   158846     314915       8392       158788     332923       8568        103
   158862     281451       8394       158788     332923       8569        104
   158823     283700       8443       158788     332923       8571        105
   158832     278550       8416       158788     332923       8573        106
   158826     280313       8321       158788     332923       8573        107
   158862     278475       8191       158788     332923       8573        108
   158828     287579       8329       158788     332923       8574        109
   158831     278570       8426       158788     332923       8575        110
   158812     279245       8343       158788     332923       8576        111
   158834     279696       8302       158788     332923       8576        112
   158821     279030       8272       158788     332923       8577        113
   158813     279595       8281       158788     332923       8577        114
   158842     281236       8320       158788     332923       8577        115
   158828     279071       8240       158788     332923       8577        116
   158812     277762       8289       158788     332923       8577        117
   158836     316260       8288       158788     332923       8578        118
   158820     280439       8216       158788     332923       8577        119
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   158854     278151       8227       158788     332923       8577        120
   158856     279570       8278       158788     332923       8577        121
   158820     277599       8280       158788     332923       8577        122
   158817     280417       8285       158788     332923       8578        123
   158836     280528       8284       158788     332923       8578        124
   158830     281836       8308       158788     332923       8578        125
   158846     282287       8235       158788     332923       8578        126
   158802     279260       8084       158788     332923       8577        127
   158829     277748       8285       158788     332923       8577        128
   158797     282115       8238       158788     332923       8577        129
   158823     279890       8264       158788     332923       8577        130
   158843     282435       8256       158788     332923       8577        131
   158803     282653       8193       158788     332923       8576        132
   158846     281912       8152       158788     332923       8575        133
   158811     286267       8273       158788     332923       8575        134
   158793     282504       8105       158788     332923       8574        135
   158803     282645       8222       158788     332923       8574        136
   158893     282463       8172       158788     332923       8573        137
   158816     282721       8220       158788     332923       8573        138
   158793     282111       8128       158788     332923       8572        139
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   158895     282404       8254       158788     332923       8572        140
   158816     281906       8165       158788     332923       8572        141
   158828     284741       8123       158788     332923       8571        142
   158803     279023       8145       158788     332923       8570        143
   158864     285006       8260       158788     332923       8570        144
   158801     292095       8158       158788     332923       8569        145
   158825     282056       8165       158788     332923       8569        146
   158828     278283       8104       158788     332923       8568        147
   158806     282645       8129       158788     332923       8567        148
   158812     281257       8033       158788     332923       8565        149
   158785     278143       8077       158785     332923       8564        150
   158813     277967       8071       158785     332923       8563        151
   158835     277609       8056       158785     332923       8562        152
   158854     274424       8030       158785     332923       8561        153
   158846     276291       8097       158785     332923       8560        154
   158801     274329       8041       158785     332923       8558        155
   158813     273914       7993       158785     332923       8557        156
   158803     278269       8039       158785     332923       8556        157
   158822     276005       8030       158785     332923       8554        158
   158828     275407       8086       158785     332923       8553        159
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   158846     276161       8064       158785     332923       8552        160
   158823     293557       8034       158785     332923       8551        161
   158818     293747       8075       158785     332923       8550        162
   158835     273236       7976       158785     332923       8548        163
   158887     291308       8082       158785     332923       8547        164
   158802     273450       7954       158785     332923       8546        165
   158791     297953       8084       158785     332923       8545        166
   158830     275599       8034       158785     332923       8544        167
   158833     283498       8152       158785     332923       8543        168
   158850     274153       8075       158785     332923       8542        169
   158844     274171       8028       158785     332923       8541        170
   158828     273098       8085       158785     332923       8540        171
   158814     291651       8048       158785     332923       8539        172
   158793     273596       8027       158785     332923       8538        173
   158801     273629       7968       158785     332923       8537        174
   158821     275390       8016       158785     332923       8536        175
   158800     274738       7988       158785     332923       8534        176
   158815     287570       7950       158785     332923       8533        177
   158858     274560       7994       158785     332923       8532        178
   158832     295338       7899       158785     332923       8530        179
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   158824     274955       7993       158785     332923       8529        180
   158830     273169       7831       158785     332923       8527        181
   158824     274661       7910       158785     332923       8525        182
   158882     274526       7982       158785     332923       8524        183
   158834     274629       8012       158785     332923       8523        184
   158836     273886       7971       158785     332923       8521        185
   158830     274058       7910       158785     332923       8520        186
   158894     295561       8062       158785     332923       8519        187
   158829     299110       7929       158785     332923       8518        188
   158811     278740       7947       158785     332923       8516        189
   158854     274135       7830       158785     332923       8514        190
   158869     272275       7819       158785     332923       8512        191
   158796     277339       7964       158785     332923       8511        192
   158888     302029       7961       158785     332923       8510        193
   158862     273311       7855       158785     332923       8507        194
   158808     271511       7769       158785     332923       8502        195
   158807     281394       7943       158785     332923       8498        196
   158823     275626       7818       158785     332923       8494        197
   158797     277487       7882       158785     332923       8490        198
   158791     285980       7754       158785     332923       8486        199

Maxtang Core i7-8665U - Caterpillar

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Attention

This benchmark utilizes Cache Allocation Technology when present.

Cache Allocation Technology (CAT)erpillar benchmark v1.1

The benchmark will execute an operation function 50000 times.
Samples are taken every 10000 test cycles.
A total of 200 samples will be measured.
Thread affinity will be set to core_id: 3

Timings are in CPU Core cycles

SampleMin:       Minimum execution time during the display update interval
SampleMax:       Maximum execution time during the display update interval
SmplJitter:      Jitter in the execution time during the display update interval
SessionMin:      Minimum execution time since the program started or statistics were reset
SessionMax:      Maximum execution time since the program started or statistics were reset
SessionJitter:   Jitter in the execution since the program started or statistics were reset
Sample:          Sample number

Priming cache...

SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   150478     151326         31       150478     151326         31          0
   150478     151840         43       150478     151840         38          1
   150478     151870         42       150478     151870         39          2
   150478     151234         35       150478     151870         38          3
   150478     151460         40       150478     151870         39          4
   150478     151294         35       150478     151870         38          5
   150476     151586         38       150476     151870         38          6
   150476     151460         38       150476     151870         38          7
   150480     151974         35       150476     151974         38          8
   150476     152170         46       150476     152170         39          9
   150478     151518         38       150476     152170         39         10
   150478     152264         40       150476     152264         39         11
   150480     151774         42       150476     152264         39         12
   150480     151124         33       150476     152264         39         13
   150476     152544         45       150476     152544         39         14
   150476     151322         33       150476     152544         39         15
   150476     151654         41       150476     152544         39         16
   150480     151938         45       150476     152544         39         17
   150476     151626         38       150476     152544         39         18
   150480     151300         35       150476     152544         39         19
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   150478     151656         42       150476     152544         39         20
   150480     151570         35       150476     152544         39         21
   150478     151684         44       150476     152544         39         22
   150478     152034         39       150476     152544         39         23
   150480     152366         40       150476     152544         39         24
   150480     152394         47       150476     152544         40         25
   150480     151248         36       150476     152544         40         26
   150476     152036         45       150476     152544         40         27
   150478     151340         40       150476     152544         40         28
   150476     151450         40       150476     152544         40         29
   150478     151972         46       150476     152544         40         30
   150478     151244         36       150476     152544         40         31
   150476     151646         40       150476     152544         40         32
   150480     152310         50       150476     152544         40         33
   150480     151134         35       150476     152544         40         34
   150478     151906         45       150476     152544         40         35
   150476     151480         38       150476     152544         40         36
   150480     152310         41       150476     152544         40         37
   150476     151716         43       150476     152544         40         38
   150476     151456         34       150476     152544         40         39
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   150476     151988         44       150476     152544         40         40
   150476     151710         38       150476     152544         40         41
   150478     152162         44       150476     152544         40         42
   150478     152168         45       150476     152544         40         43
   150476     151654         37       150476     152544         40         44
   150476     151854         42       150476     152544         40         45
   150474     151770         36       150474     152544         40         46
   150478     151638         40       150474     152544         40         47
   150476     151720         43       150474     152544         40         48
   150480     151494         37       150474     152544         40         49
   150476     151642         38       150474     152544         40         50
   150480     152024         46       150474     152544         40         51
   150476     151098         33       150474     152544         40         52
   150480     152060         45       150474     152544         40         53
   150476     151630         37       150474     152544         40         54
   150480     151474         36       150474     152544         40         55
   150476     152020         44       150474     152544         40         56
   150476     152026         38       150474     152544         40         57
   150478     151816         40       150474     152544         40         58
   150478     151496         38       150474     152544         40         59
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   150474     152004         38       150474     152544         40         60
   150476     151618         46       150474     152544         40         61
   150476     151502         38       150474     152544         40         62
   150478     152512         44       150474     152544         40         63
   150478     151468         42       150474     152544         40         64
   150476     151124         33       150474     152544         40         65
   150478     151636         41       150474     152544         40         66
   150478     151700         42       150474     152544         40         67
   150478     151498         39       150474     152544         40         68
   150478     151478         44       150474     152544         40         69
   150476     151284         34       150474     152544         40         70
   150476     152770         48       150474     152770         40         71
   150480     151772         40       150474     152770         40         72
   150476     151838         39       150474     152770         40         73
   150480     151654         42       150474     152770         40         74
   150480     151950         41       150474     152770         40         75
   150480     151456         38       150474     152770         40         76
   150478     151478         41       150474     152770         40         77
   150478     151516         41       150474     152770         40         78
   150478     151856         42       150474     152770         40         79
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   150480     152074         40       150474     152770         40         80
   150478     151398         36       150474     152770         40         81
   150476     151790         44       150474     152770         40         82
   150476     151738         36       150474     152770         40         83
   150476     152096         46       150474     152770         40         84
   150480     151470         38       150474     152770         40         85
   150476     151750         37       150474     152770         40         86
   150476     152860         50       150474     152860         41         87
   150480     151304         33       150474     152860         40         88
   150478     151662         41       150474     152860         40         89
   150474     152166         41       150474     152860         40         90
   150476     151990         38       150474     152860         40         91
   150478     151628         44       150474     152860         40         92
   150478     151824         41       150474     152860         40         93
   150480     151664         37       150474     152860         40         94
   150478     151854         43       150474     152860         40         95
   150480     151214         34       150474     152860         40         96
   150478     151850         43       150474     152860         40         97
   150478     151668         38       150474     152860         40         98
   150478     152164         38       150474     152860         40         99
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   150480     151646         42       150474     152860         40        100
   150480     151370         38       150474     152860         40        101
   150480     151776         40       150474     152860         40        102
   150476     151784         41       150474     152860         40        103
   150478     151510         38       150474     152860         40        104
   150478     152022         46       150474     152860         40        105
   150474     151562         38       150474     152860         40        106
   150478     152028         39       150474     152860         40        107
   150478     151968         45       150474     152860         40        108
   150478     151272         34       150474     152860         40        109
   150476     152156         44       150474     152860         40        110
   150478     151432         39       150474     152860         40        111
   150476     151838         38       150474     152860         40        112
   150476     151556         40       150474     152860         40        113
   150480     151486         38       150474     152860         40        114
   150476     151592         43       150474     152860         40        115
   150478     151202         35       150474     152860         40        116
   150478     152724         41       150474     152860         40        117
   150476     151858         45       150474     152860         40        118
   150480     151380         35       150474     152860         40        119
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   150476     152346         46       150474     152860         40        120
   150476     151638         38       150474     152860         40        121
   150478     152200         41       150474     152860         40        122
   150480     151764         40       150474     152860         40        123
   150478     151408         38       150474     152860         40        124
   150476     152046         42       150474     152860         40        125
   150476     151784         43       150474     152860         40        126
   150476     151140         32       150474     152860         40        127
   150476     151974         46       150474     152860         40        128
   150480     151810         41       150474     152860         40        129
   150474     151602         37       150474     152860         40        130
   150478     152482         47       150474     152860         40        131
   150478     151302         35       150474     152860         40        132
   150478     152030         42       150474     152860         40        133
   150480     151406         39       150474     152860         40        134
   150480     151652         38       150474     152860         40        135
   150474     151960         46       150474     152860         40        136
   150478     151606         40       150474     152860         40        137
   150476     151852         36       150474     152860         40        138
   150476     152242         46       150474     152860         40        139
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   150476     151412         34       150474     152860         40        140
   150476     151820         42       150474     152860         40        141
   150478     151484         39       150474     152860         40        142
   150476     151340         38       150474     152860         40        143
   150480     151342         41       150474     152860         40        144
   150476     151446         37       150474     152860         40        145
   150476     151650         40       150474     152860         40        146
   150478     151442         40       150474     152860         40        147
   150478     151820         41       150474     152860         40        148
   150478     151648         44       150474     152860         40        149
   150478     151756         40       150474     152860         40        150
   150480     151766         40       150474     152860         40        151
   150480     151986         44       150474     152860         40        152
   150478     151068         31       150474     152860         40        153
   150478     151598         43       150474     152860         40        154
   150478     151106         35       150474     152860         40        155
   150478     152208         48       150474     152860         40        156
   150476     152212         49       150474     152860         40        157
   150478     151110         33       150474     152860         40        158
   150480     152026         44       150474     152860         40        159
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   150478     151668         38       150474     152860         40        160
   150478     151404         36       150474     152860         40        161
   150478     152540         47       150474     152860         40        162
   150480     151984         37       150474     152860         40        163
   150476     151662         39       150474     152860         40        164
   150478     151598         37       150474     152860         40        165
   150478     151818         40       150474     152860         40        166
   150476     152134         46       150474     152860         40        167
   150474     151280         38       150474     152860         40        168
   150470     151812         38       150470     152860         40        169
   150478     151832         44       150470     152860         40        170
   150478     151228         32       150470     152860         40        171
   150478     151448         41       150470     152860         40        172
   150476     152048         42       150470     152860         40        173
   150476     151272         37       150470     152860         40        174
   150478     152278         43       150470     152860         40        175
   150478     151480         37       150470     152860         40        176
   150478     151494         41       150470     152860         40        177
   150478     151444         37       150470     152860         40        178
   150478     152268         41       150470     152860         40        179
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   150476     151632         44       150470     152860         40        180
   150478     151470         39       150470     152860         40        181
   150478     151606         37       150470     152860         40        182
   150476     151766         44       150470     152860         40        183
   150478     151152         33       150470     152860         40        184
   150480     152050         45       150470     152860         40        185
   150478     151778         38       150470     152860         40        186
   150480     151650         38       150470     152860         40        187
   150478     151826         42       150470     152860         40        188
   150478     151662         39       150470     152860         40        189
   150480     152216         44       150470     152860         40        190
   150478     151274         38       150470     152860         40        191
   150478     152196         40       150470     152860         40        192
   150480     151736         41       150470     152860         40        193
   150480     151746         37       150470     152860         40        194
   150478     152260         44       150470     152860         40        195
   150476     152590         45       150470     152860         40        196
   150480     151504         37       150470     152860         40        197
   150478     152438         46       150470     152860         40        198
   150478     151374         38       150470     152860         40        199

Vecow Core i7-1186G7E - Caterpillar

Click to toggle results

Attention

This benchmark utilizes (CAT) when present.

Cache Allocation Technology (CAT)erpillar benchmark v1.1

The benchmark will execute an operation function 50000 times.
Samples are taken every 10000 test cycles.
A total of 200 samples will be measured.
Thread affinity will be set to core_id: 3

Timings are in CPU Core cycles

SampleMin:       Minimum execution time during the display update interval
SampleMax:       Maximum execution time during the display update interval
SmplJitter:      Jitter in the execution time during the display update interval
SessionMin:      Minimum execution time since the program started or statistics were reset
SessionMax:      Maximum execution time since the program started or statistics were reset
SessionJitter:   Jitter in the execution since the program started or statistics were reset
Sample:          Sample number

Priming cache...

SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   136395     146446        369       136395     146446        369          0
   136395     141012        386       136395     146446        378          1
   136395     141343        358       136395     146446        372          2
   136360     140298        359       136360     146446        370          3
   136362     140633        378       136360     146446        374          4
   136355     142378        370       136355     146446        376          5
   136372     141024        367       136355     146446        378          6
   136362     141616        374       136355     146446        380          7
   136360     143380        371       136355     146446        382          8
   136358     140728        376       136355     146446        384          9
   136379     143082        383       136355     146446        387         10
   136376     153393        404       136355     153393        391         11
   136352     142630        386       136352     153393        393         12
   136366     141859        370       136352     153393        394         13
   136360     140769        372       136352     153393        395         14
   136374     141577        368       136352     153393        396         15
   136366     150718        396       136352     153393        398         16
   136366     143120        383       136352     153393        400         17
   136376     140480        372       136352     153393        400         18
   136360     143530        373       136352     153393        401         19
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   136362     142060        374       136352     153393        402         20
   136356     140867        384       136352     153393        403         21
   136366     148585        386       136352     153393        404         22
   136360     140931        367       136352     153393        405         23
   136364     145293        374       136352     153393        405         24
   136366     143292        392       136352     153393        406         25
   136364     140314        365       136352     153393        407         26
   136355     141676        368       136352     153393        407         27
   136376     141656        392       136352     153393        408         28
   136362     152236        428       136352     153393        410         29
   136352     155089        415       136352     155089        412         30
   136368     142218        366       136352     155089        412         31
   136362     143763        382       136352     155089        412         32
   136370     145814        387       136352     155089        413         33
   136358     141210        364       136352     155089        413         34
   136358     141022        381       136352     155089        413         35
   136358     143096        376       136352     155089        414         36
   136368     145702        385       136352     155089        414         37
   136368     140543        370       136352     155089        414         38
   136356     141539        393       136352     155089        415         39
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   136355     142396        364       136352     155089        415         40
   136374     151165        410       136352     155089        416         41
   136358     141168        376       136352     155089        416         42
   136372     140953        354       136352     155089        416         43
   136364     149419        420       136352     155089        417         44
   136383     142563        372       136352     155089        417         45
   136370     144334        382       136352     155089        417         46
   136358     153174        397       136352     155089        418         47
   136377     142995        376       136352     155089        418         48
   136368     142290        382       136352     155089        418         49
   136376     152223        400       136352     155089        419         50
   136358     140580        381       136352     155089        419         51
   136374     143857        380       136352     155089        419         52
   136368     140896        367       136352     155089        419         53
   136371     142820        372       136352     155089        419         54
   136362     149059        430       136352     155089        420         55
   136366     141952        364       136352     155089        420         56
   136354     141648        381       136352     155089        420         57
   136359     147346        379       136352     155089        420         58
   136368     146929        424       136352     155089        421         59
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   136364     141580        381       136352     155089        421         60
   136364     141750        375       136352     155089        421         61
   136358     140774        366       136352     155089        421         62
   136370     152706        419       136352     155089        421         63
   136360     140815        367       136352     155089        421         64
   136376     149610        421       136352     155089        422         65
   136354     143313        376       136352     155089        422         66
   136354     143995        386       136352     155089        422         67
   136360     152954        435       136352     155089        423         68
   136353     152602        408       136352     155089        424         69
   136356     142133        381       136352     155089        424         70
   136366     146894        407       136352     155089        424         71
   136354     142012        388       136352     155089        424         72
   136364     148853        403       136352     155089        424         73
   136368     140884        371       136352     155089        424         74
   136381     140802        375       136352     155089        424         75
   136356     141292        376       136352     155089        424         76
   136362     141223        389       136352     155089        424         77
   136360     144528        382       136352     155089        424         78
   136366     148135        399       136352     155089        425         79
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   136374     148965        403       136352     155089        425         80
   136358     150336        392       136352     155089        425         81
   136366     148221        401       136352     155089        425         82
   136354     147739        392       136352     155089        426         83
   136360     144384        381       136352     155089        426         84
   136362     141217        351       136352     155089        425         85
   136368     141417        380       136352     155089        425         86
   136362     140797        383       136352     155089        425         87
   136374     140686        366       136352     155089        425         88
   136352     151973        411       136352     155089        426         89
   136364     141981        375       136352     155089        426         90
   136374     154495        414       136352     155089        426         91
   136354     149182        412       136352     155089        426         92
   136360     141352        372       136352     155089        426         93
   136356     140626        364       136352     155089        426         94
   136366     141971        367       136352     155089        426         95
   136368     140979        374       136352     155089        426         96
   136364     145803        397       136352     155089        426         97
   136360     141001        375       136352     155089        426         98
   136370     140479        356       136352     155089        426         99
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   136364     142480        376       136352     155089        426        100
   136356     142879        385       136352     155089        426        101
   136358     141192        373       136352     155089        426        102
   136378     144039        374       136352     155089        426        103
   136364     142125        379       136352     155089        426        104
   136364     141064        377       136352     155089        426        105
   136362     141324        371       136352     155089        426        106
   136355     142452        388       136352     155089        426        107
   136376     153310        409       136352     155089        426        108
   136358     141614        367       136352     155089        426        109
   136380     147644        399       136352     155089        426        110
   136370     142530        376       136352     155089        426        111
   136379     140996        374       136352     155089        426        112
   136362     140685        381       136352     155089        426        113
   136354     147442        393       136352     155089        426        114
   136356     141705        374       136352     155089        426        115
   136354     142381        372       136352     155089        426        116
   136364     140570        369       136352     155089        426        117
   136362     148336        382       136352     155089        426        118
   136366     141198        372       136352     155089        426        119
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   136366     151327        408       136352     155089        426        120
   136362     144094        390       136352     155089        426        121
   136374     149567        389       136352     155089        427        122
   136362     140945        380       136352     155089        427        123
   136370     142403        390       136352     155089        427        124
   136368     142794        376       136352     155089        427        125
   136374     153215        422       136352     155089        427        126
   136356     141251        369       136352     155089        427        127
   136364     147890        390       136352     155089        427        128
   136362     140780        371       136352     155089        427        129
   136378     142121        381       136352     155089        427        130
   136370     143155        380       136352     155089        427        131
   136368     140971        377       136352     155089        427        132
   136370     141103        370       136352     155089        427        133
   136358     145377        381       136352     155089        427        134
   136360     142313        388       136352     155089        427        135
   136360     142025        372       136352     155089        427        136
   136357     141403        380       136352     155089        427        137
   136372     140586        375       136352     155089        427        138
   136368     140684        369       136352     155089        427        139
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   136354     140679        373       136352     155089        427        140
   136366     141472        370       136352     155089        427        141
   136360     145101        377       136352     155089        427        142
   136364     140983        380       136352     155089        427        143
   136358     140874        372       136352     155089        427        144
   136358     140146        360       136352     155089        426        145
   136358     144062        375       136352     155089        426        146
   136364     141206        375       136352     155089        426        147
   136368     145992        382       136352     155089        426        148
   136348     140833        373       136348     155089        426        149
   136358     140694        364       136348     155089        426        150
   136362     140452        385       136348     155089        426        151
   136360     144654        392       136348     155089        426        152
   136362     140349        364       136348     155089        426        153
   136360     140596        365       136348     155089        426        154
   136355     144021        393       136348     155089        426        155
   136360     141736        366       136348     155089        426        156
   136360     141261        385       136348     155089        426        157
   136362     140744        381       136348     155089        426        158
   136370     145376        387       136348     155089        426        159
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   136356     141011        382       136348     155089        426        160
   136368     143591        378       136348     155089        426        161
   136360     143867        389       136348     155089        426        162
   136355     142848        390       136348     155089        426        163
   136358     142287        390       136348     155089        427        164
   136381     147856        392       136348     155089        427        165
   136364     140604        377       136348     155089        427        166
   136352     141478        369       136348     155089        427        167
   136372     140468        376       136348     155089        427        168
   136354     151761        411       136348     155089        427        169
   136356     146317        408       136348     155089        427        170
   136364     145811        402       136348     155089        427        171
   136382     152696        418       136348     155089        427        172
   136367     143171        386       136348     155089        427        173
   136364     140770        385       136348     155089        427        174
   136352     147326        407       136348     155089        427        175
   136376     140770        379       136348     155089        427        176
   136360     146953        396       136348     155089        427        177
   136358     140598        378       136348     155089        427        178
   136360     148474        431       136348     155089        428        179
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   136368     150563        428       136348     155089        428        180
   136362     141064        378       136348     155089        428        181
   136362     141417        368       136348     155089        428        182
   136354     150026        409       136348     155089        428        183
   136360     150269        403       136348     155089        428        184
   136350     144079        395       136348     155089        428        185
   136356     144343        394       136348     155089        428        186
   136352     142871        395       136348     155089        428        187
   136360     146288        388       136348     155089        428        188
   136351     140815        375       136348     155089        428        189
   136362     141105        387       136348     155089        428        190
   136366     142253        384       136348     155089        428        191
   136353     141061        376       136348     155089        428        192
   136356     147379        401       136348     155089        428        193
   136366     142115        389       136348     155089        428        194
   136352     146280        380       136348     155089        428        195
   136360     141109        388       136348     155089        428        196
   136360     148910        431       136348     155089        429        197
   136366     149155        399       136348     155089        429        198
   136359     141926        388       136348     155089        429        199

Vecow Core i7-1185G7E - Caterpillar

Click to toggle results

Attention

This benchmark utilizes (CAT) when present.

Cache Allocation Technology (CAT)erpillar benchmark v1.1

The benchmark will execute an operation function 50000 times.
Samples are taken every 10000 test cycles.
A total of 200 samples will be measured.
Thread affinity will be set to core_id: 3

Timings are in CPU Core cycles

SampleMin:       Minimum execution time during the display update interval
SampleMax:       Maximum execution time during the display update interval
SmplJitter:      Jitter in the execution time during the display update interval
SessionMin:      Minimum execution time since the program started or statistics were reset
SessionMax:      Maximum execution time since the program started or statistics were reset
SessionJitter:   Jitter in the execution since the program started or statistics were reset
Sample:          Sample number

Priming cache...

SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   136395     146446        369       136395     146446        369          0
   136395     141012        386       136395     146446        378          1
   136395     141343        358       136395     146446        372          2
   136360     140298        359       136360     146446        370          3
   136362     140633        378       136360     146446        374          4
   136355     142378        370       136355     146446        376          5
   136372     141024        367       136355     146446        378          6
   136362     141616        374       136355     146446        380          7
   136360     143380        371       136355     146446        382          8
   136358     140728        376       136355     146446        384          9
   136379     143082        383       136355     146446        387         10
   136376     153393        404       136355     153393        391         11
   136352     142630        386       136352     153393        393         12
   136366     141859        370       136352     153393        394         13
   136360     140769        372       136352     153393        395         14
   136374     141577        368       136352     153393        396         15
   136366     150718        396       136352     153393        398         16
   136366     143120        383       136352     153393        400         17
   136376     140480        372       136352     153393        400         18
   136360     143530        373       136352     153393        401         19
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   136362     142060        374       136352     153393        402         20
   136356     140867        384       136352     153393        403         21
   136366     148585        386       136352     153393        404         22
   136360     140931        367       136352     153393        405         23
   136364     145293        374       136352     153393        405         24
   136366     143292        392       136352     153393        406         25
   136364     140314        365       136352     153393        407         26
   136355     141676        368       136352     153393        407         27
   136376     141656        392       136352     153393        408         28
   136362     152236        428       136352     153393        410         29
   136352     155089        415       136352     155089        412         30
   136368     142218        366       136352     155089        412         31
   136362     143763        382       136352     155089        412         32
   136370     145814        387       136352     155089        413         33
   136358     141210        364       136352     155089        413         34
   136358     141022        381       136352     155089        413         35
   136358     143096        376       136352     155089        414         36
   136368     145702        385       136352     155089        414         37
   136368     140543        370       136352     155089        414         38
   136356     141539        393       136352     155089        415         39
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   136355     142396        364       136352     155089        415         40
   136374     151165        410       136352     155089        416         41
   136358     141168        376       136352     155089        416         42
   136372     140953        354       136352     155089        416         43
   136364     149419        420       136352     155089        417         44
   136383     142563        372       136352     155089        417         45
   136370     144334        382       136352     155089        417         46
   136358     153174        397       136352     155089        418         47
   136377     142995        376       136352     155089        418         48
   136368     142290        382       136352     155089        418         49
   136376     152223        400       136352     155089        419         50
   136358     140580        381       136352     155089        419         51
   136374     143857        380       136352     155089        419         52
   136368     140896        367       136352     155089        419         53
   136371     142820        372       136352     155089        419         54
   136362     149059        430       136352     155089        420         55
   136366     141952        364       136352     155089        420         56
   136354     141648        381       136352     155089        420         57
   136359     147346        379       136352     155089        420         58
   136368     146929        424       136352     155089        421         59
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   136364     141580        381       136352     155089        421         60
   136364     141750        375       136352     155089        421         61
   136358     140774        366       136352     155089        421         62
   136370     152706        419       136352     155089        421         63
   136360     140815        367       136352     155089        421         64
   136376     149610        421       136352     155089        422         65
   136354     143313        376       136352     155089        422         66
   136354     143995        386       136352     155089        422         67
   136360     152954        435       136352     155089        423         68
   136353     152602        408       136352     155089        424         69
   136356     142133        381       136352     155089        424         70
   136366     146894        407       136352     155089        424         71
   136354     142012        388       136352     155089        424         72
   136364     148853        403       136352     155089        424         73
   136368     140884        371       136352     155089        424         74
   136381     140802        375       136352     155089        424         75
   136356     141292        376       136352     155089        424         76
   136362     141223        389       136352     155089        424         77
   136360     144528        382       136352     155089        424         78
   136366     148135        399       136352     155089        425         79
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   136374     148965        403       136352     155089        425         80
   136358     150336        392       136352     155089        425         81
   136366     148221        401       136352     155089        425         82
   136354     147739        392       136352     155089        426         83
   136360     144384        381       136352     155089        426         84
   136362     141217        351       136352     155089        425         85
   136368     141417        380       136352     155089        425         86
   136362     140797        383       136352     155089        425         87
   136374     140686        366       136352     155089        425         88
   136352     151973        411       136352     155089        426         89
   136364     141981        375       136352     155089        426         90
   136374     154495        414       136352     155089        426         91
   136354     149182        412       136352     155089        426         92
   136360     141352        372       136352     155089        426         93
   136356     140626        364       136352     155089        426         94
   136366     141971        367       136352     155089        426         95
   136368     140979        374       136352     155089        426         96
   136364     145803        397       136352     155089        426         97
   136360     141001        375       136352     155089        426         98
   136370     140479        356       136352     155089        426         99
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   136364     142480        376       136352     155089        426        100
   136356     142879        385       136352     155089        426        101
   136358     141192        373       136352     155089        426        102
   136378     144039        374       136352     155089        426        103
   136364     142125        379       136352     155089        426        104
   136364     141064        377       136352     155089        426        105
   136362     141324        371       136352     155089        426        106
   136355     142452        388       136352     155089        426        107
   136376     153310        409       136352     155089        426        108
   136358     141614        367       136352     155089        426        109
   136380     147644        399       136352     155089        426        110
   136370     142530        376       136352     155089        426        111
   136379     140996        374       136352     155089        426        112
   136362     140685        381       136352     155089        426        113
   136354     147442        393       136352     155089        426        114
   136356     141705        374       136352     155089        426        115
   136354     142381        372       136352     155089        426        116
   136364     140570        369       136352     155089        426        117
   136362     148336        382       136352     155089        426        118
   136366     141198        372       136352     155089        426        119
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   136366     151327        408       136352     155089        426        120
   136362     144094        390       136352     155089        426        121
   136374     149567        389       136352     155089        427        122
   136362     140945        380       136352     155089        427        123
   136370     142403        390       136352     155089        427        124
   136368     142794        376       136352     155089        427        125
   136374     153215        422       136352     155089        427        126
   136356     141251        369       136352     155089        427        127
   136364     147890        390       136352     155089        427        128
   136362     140780        371       136352     155089        427        129
   136378     142121        381       136352     155089        427        130
   136370     143155        380       136352     155089        427        131
   136368     140971        377       136352     155089        427        132
   136370     141103        370       136352     155089        427        133
   136358     145377        381       136352     155089        427        134
   136360     142313        388       136352     155089        427        135
   136360     142025        372       136352     155089        427        136
   136357     141403        380       136352     155089        427        137
   136372     140586        375       136352     155089        427        138
   136368     140684        369       136352     155089        427        139
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   136354     140679        373       136352     155089        427        140
   136366     141472        370       136352     155089        427        141
   136360     145101        377       136352     155089        427        142
   136364     140983        380       136352     155089        427        143
   136358     140874        372       136352     155089        427        144
   136358     140146        360       136352     155089        426        145
   136358     144062        375       136352     155089        426        146
   136364     141206        375       136352     155089        426        147
   136368     145992        382       136352     155089        426        148
   136348     140833        373       136348     155089        426        149
   136358     140694        364       136348     155089        426        150
   136362     140452        385       136348     155089        426        151
   136360     144654        392       136348     155089        426        152
   136362     140349        364       136348     155089        426        153
   136360     140596        365       136348     155089        426        154
   136355     144021        393       136348     155089        426        155
   136360     141736        366       136348     155089        426        156
   136360     141261        385       136348     155089        426        157
   136362     140744        381       136348     155089        426        158
   136370     145376        387       136348     155089        426        159
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   136356     141011        382       136348     155089        426        160
   136368     143591        378       136348     155089        426        161
   136360     143867        389       136348     155089        426        162
   136355     142848        390       136348     155089        426        163
   136358     142287        390       136348     155089        427        164
   136381     147856        392       136348     155089        427        165
   136364     140604        377       136348     155089        427        166
   136352     141478        369       136348     155089        427        167
   136372     140468        376       136348     155089        427        168
   136354     151761        411       136348     155089        427        169
   136356     146317        408       136348     155089        427        170
   136364     145811        402       136348     155089        427        171
   136382     152696        418       136348     155089        427        172
   136367     143171        386       136348     155089        427        173
   136364     140770        385       136348     155089        427        174
   136352     147326        407       136348     155089        427        175
   136376     140770        379       136348     155089        427        176
   136360     146953        396       136348     155089        427        177
   136358     140598        378       136348     155089        427        178
   136360     148474        431       136348     155089        428        179
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   136368     150563        428       136348     155089        428        180
   136362     141064        378       136348     155089        428        181
   136362     141417        368       136348     155089        428        182
   136354     150026        409       136348     155089        428        183
   136360     150269        403       136348     155089        428        184
   136350     144079        395       136348     155089        428        185
   136356     144343        394       136348     155089        428        186
   136352     142871        395       136348     155089        428        187
   136360     146288        388       136348     155089        428        188
   136351     140815        375       136348     155089        428        189
   136362     141105        387       136348     155089        428        190
   136366     142253        384       136348     155089        428        191
   136353     141061        376       136348     155089        428        192
   136356     147379        401       136348     155089        428        193
   136366     142115        389       136348     155089        428        194
   136352     146280        380       136348     155089        428        195
   136360     141109        388       136348     155089        428        196
   136360     148910        431       136348     155089        429        197
   136366     149155        399       136348     155089        429        198
   136359     141926        388       136348     155089        429        199

Karbon 700 Core i7-9700TE - Caterpillar

Click to toggle results

Attention

This benchmark utilizes CAT when present.

Cache Allocation Technology (CAT)erpillar benchmark v1.1

The benchmark will execute an operation function 50000 times.
Samples are taken every 10000 test cycles.
A total of 200 samples will be measured.
Thread affinity will be set to core_id: 3

Timings are in CPU Core cycles

SampleMin:       Minimum execution time during the display update interval
SampleMax:       Maximum execution time during the display update interval
SmplJitter:      Jitter in the execution time during the display update interval
SessionMin:      Minimum execution time since the program started or statistics were reset
SessionMax:      Maximum execution time since the program started or statistics were reset
SessionJitter:   Jitter in the execution since the program started or statistics were reset
Sample:          Sample number

Priming cache...

SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   71824      72655         27        71824      72655         27          0
   71803      73008         34        71803      73008         32          1
   71802      73160         31        71802      73160         32          2
   71805      72653         29        71802      73160         32          3
   71807      72569         34        71802      73160         32          4
   71802      72756         29        71802      73160         32          5
   71805      72675         30        71802      73160         32          6
   71804      72892         32        71802      73160         32          7
   71809      72904         31        71802      73160         33          8
   71805      72896         35        71802      73160         33          9
   71808      72740         30        71802      73160         33         10
   71805      72845         30        71802      73160         33         11
   71807      73027         34        71802      73160         33         12
   71807      72631         29        71802      73160         33         13
   71808      72685         38        71802      73160         33         14
   71809      72625         29        71802      73160         33         15
   71805      72567         31        71802      73160         33         16
   71797      73198         38        71797      73198         34         17
   71796      72294         25        71796      73198         34         18
   71795      72689         36        71795      73198         34         19
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   71796      73125         36        71795      73198         35         20
   71795      72471         30        71795      73198         35         21
   71789      72406         31        71789      73198         35         22
   71765      72669         30        71765      73198         36         23
   71791      73701         36        71765      73701         36         24
   71801      72894         32        71765      73701         36         25
   71796      72774         30        71765      73701         36         26
   71797      72945         36        71765      73701         37         27
   71795      72377         27        71765      73701         37         28
   71796      72750         34        71765      73701         37         29
   71791      72906         30        71765      73701         37         30
   71793      72695         28        71765      73701         37         31
   71795      72999         36        71765      73701         37         32
   71795      72922         31        71765      73701         37         33
   71791      73208         36        71765      73701         37         34
   71759      73371         37        71759      73701         38         35
   71795      72618         28        71759      73701         38         36
   71794      73237         35        71759      73701         38         37
   71795      72590         30        71759      73701         38         38
   71765      72468         30        71759      73701         38         39
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   71796      72831         36        71759      73701         38         40
   71797      72265         30        71759      73701         38         41
   71779      73443         39        71759      73701         38         42
   71795      73807         36        71759      73807         38         43
   71799      72657         30        71759      73807         38         44
   71769      72784         35        71759      73807         39         45
   71794      72511         29        71759      73807         39         46
   71795      72790         36        71759      73807         39         47
   71795      72961         33        71759      73807         39         48
   71794      72924         31        71759      73807         39         49
   71799      72641         34        71759      73807         39         50
   71794      72241         26        71759      73807         39         51
   71802      72527         32        71759      73807         39         52
   71780      72762         33        71759      73807         39         53
   71773      72531         30        71759      73807         39         54
   71798      72610         31        71759      73807         39         55
   71796      72920         31        71759      73807         39         56
   71797      72724         36        71759      73807         39         57
   71763      72659         29        71759      73807         39         58
   71798      72606         33        71759      73807         39         59
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   71793      73229         37        71759      73807         39         60
   71791      72574         29        71759      73807         39         61
   71765      72724         36        71759      73807         39         62
   71799      73127         35        71759      73807         39         63
   71795      72792         32        71759      73807         39         64
   71795      72771         35        71759      73807         39         65
   71795      72882         29        71759      73807         39         66
   71797      72841         34        71759      73807         39         67
   71795      73036         36        71759      73807         39         68
   71797      72400         28        71759      73807         39         69
   71795      72983         38        71759      73807         39         70
   71795      72926         34        71759      73807         39         71
   71763      72665         32        71759      73807         39         72
   71796      73200         35        71759      73807         39         73
   71796      72694         28        71759      73807         39         74
   71777      72869         36        71759      73807         40         75
   71797      72596         30        71759      73807         39         76
   71798      72818         32        71759      73807         39         77
   71792      72551         34        71759      73807         39         78
   71796      72480         29        71759      73807         39         79
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   71773      72829         37        71759      73807         40         80
   71796      72851         31        71759      73807         40         81
   71801      75378         47        71759      75378         40         82
   71799      72994         37        71759      75378         40         83
   71802      72621         26        71759      75378         40         84
   71797      73210         35        71759      75378         40         85
   71771      73016         35        71759      75378         40         86
   71795      72511         30        71759      75378         40         87
   71769      72541         36        71759      75378         40         88
   71795      72673         29        71759      75378         40         89
   71793      72628         32        71759      75378         40         90
   71795      72582         29        71759      75378         40         91
   71797      72716         29        71759      75378         40         92
   71798      73385         35        71759      75378         40         93
   71791      73139         34        71759      75378         40         94
   71798      73044         32        71759      75378         40         95
   71769      72945         35        71759      75378         40         96
   71795      72302         26        71759      75378         40         97
   71798      73038         36        71759      75378         40         98
   71796      72793         33        71759      75378         40         99
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   71797      72673         32        71759      75378         40        100
   71795      73094         38        71759      75378         40        101
   71796      72199         27        71759      75378         40        102
   71771      73087         40        71759      75378         40        103
   71795      72854         33        71759      75378         40        104
   71802      72507         29        71759      75378         40        105
   71796      73034         37        71759      75378         40        106
   71792      72322         26        71759      75378         40        107
   71796      73066         36        71759      75378         40        108
   71761      72959         33        71759      75378         40        109
   71796      72890         32        71759      75378         40        110
   71795      73640         37        71759      75378         40        111
   71797      72448         26        71759      75378         40        112
   71794      72732         34        71759      75378         40        113
   71793      72834         32        71759      75378         40        114
   71792      72503         30        71759      75378         40        115
   71792      73135         38        71759      75378         40        116
   71767      72624         32        71759      75378         40        117
   71799      75421         59        71759      75421         40        118
   71805      72787         31        71759      75421         40        119
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   71805      72430         27        71759      75421         40        120
   71773      73070         38        71759      75421         40        121
   71793      72425         30        71759      75421         40        122
   71797      72752         32        71759      75421         40        123
   71799      72764         33        71759      75421         40        124
   71795      72811         28        71759      75421         40        125
   71791      74819         46        71759      75421         40        126
   71796      72989         32        71759      75421         40        127
   71799      72746         32        71759      75421         40        128
   71797      72910         34        71759      75421         40        129
   71799      72653         29        71759      75421         40        130
   71775      73064         38        71759      75421         40        131
   71798      72529         31        71759      75421         40        132
   71790      73188         35        71759      75421         40        133
   71797      72898         35        71759      75421         40        134
   71798      72586         28        71759      75421         40        135
   71802      72555         32        71759      75421         40        136
   71795      72517         30        71759      75421         40        137
   71769      72987         33        71759      75421         40        138
   71791      72719         33        71759      75421         40        139
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   71806      72483         26        71759      75421         40        140
   71796      72583         32        71759      75421         40        141
   71796      72993         36        71759      75421         40        142
   71798      72626         29        71759      75421         40        143
   71795      72781         35        71759      75421         40        144
   71796      72473         29        71759      75421         40        145
   71783      73070         38        71759      75421         40        146
   71802      72671         30        71759      75421         40        147
   71801      72771         33        71759      75421         40        148
   71799      73133         36        71759      75421         40        149
   71802      73301         36        71759      75421         40        150
   71802      72883         33        71759      75421         40        151
   71803      75427         61        71759      75427         40        152
   71801      72551         29        71759      75427         40        153
   71793      72787         36        71759      75427         40        154
   71787      72759         33        71759      75427         40        155
   71796      72728         29        71759      75427         40        156
   71802      73161         38        71759      75427         40        157
   71795      72675         30        71759      75427         40        158
   71795      73266         37        71759      75427         40        159
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   71807      72722         31        71759      75427         40        160
   71795      72610         31        71759      75427         40        161
   71795      72819         33        71759      75427         40        162
   71803      72314         26        71759      75427         40        163
   71799      72798         36        71759      75427         40        164
   71794      72908         32        71759      75427         40        165
   71795      72474         28        71759      75427         40        166
   71801      72673         34        71759      75427         40        167
   71795      72710         29        71759      75427         40        168
   71791      72556         32        71759      75427         40        169
   71800      72831         32        71759      75427         40        170
   71795      72819         33        71759      75427         40        171
   71797      73044         36        71759      75427         40        172
   71795      72537         29        71759      75427         40        173
   71791      72638         31        71759      75427         40        174
   71797      72765         33        71759      75427         40        175
   71793      72427         28        71759      75427         40        176
   71797      73006         36        71759      75427         40        177
   71804      72825         31        71759      75427         40        178
   71799      72631         30        71759      75427         40        179
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   71790      72853         32        71759      75427         40        180
   71795      72450         28        71759      75427         40        181
   71793      72671         35        71759      75427         40        182
   71792      72847         32        71759      75427         40        183
   71797      72548         30        71759      75427         40        184
   71767      72934         37        71759      75427         40        185
   71797      72505         29        71759      75427         40        186
   71775      72835         34        71759      75427         40        187
   71799      73044         33        71759      75427         40        188
   71795      72586         31        71759      75427         40        189
   71791      72773         33        71759      75427         40        190
   71777      72357         25        71759      75427         40        191
   71807      72754         35        71759      75427         40        192
   71795      72533         30        71759      75427         40        193
   71793      72794         32        71759      75427         40        194
   71796      72821         37        71759      75427         40        195
   71794      72568         29        71759      75427         40        196
   71767      73277         36        71759      75427         40        197
   71798      73147         31        71759      75427         40        198
   71799      73123         33        71759      75427         40        199

TGL-RVP Core i7-1185GRE - Caterpillar

Click to toggle results

Attention

This benchmark utilizes CAT when present.

Cache Allocation Technology (CAT)erpillar benchmark v1.1

The benchmark will execute an operation function 50000 times.
Samples are taken every 10000 test cycles.
A total of 200 samples will be measured.
Thread affinity will be set to core_id: 3

Timings are in CPU Core cycles

SampleMin:       Minimum execution time during the display update interval
SampleMax:       Maximum execution time during the display update interval
SmplJitter:      Jitter in the execution time during the display update interval
SessionMin:      Minimum execution time since the program started or statistics were reset
SessionMax:      Maximum execution time since the program started or statistics were reset
SessionJitter:   Jitter in the execution since the program started or statistics were reset
Sample:          Sample number

Priming cache...

SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   136533     137899         51       136533     137899         51          0
   136451     138089         58       136451     138089         55          1
   136506     138128         55       136451     138128         55          2
   136530     138374         57       136451     138374         56          3
   136464     138779         73       136451     138779         60          4
   136527     139488         65       136451     139488         61          5
   136534     138138         49       136451     139488         59          6
   136425     138159         49       136425     139488         58          7
   136532     137840         48       136425     139488         57          8
   136463     138666         75       136425     139488         60          9
   136520     138440         49       136425     139488         60         10
   136510     137822         46       136425     139488         59         11
   136506     137989         51       136425     139488         59         12
   136469     137974         49       136425     139488         59         13
   136508     138712         58       136425     139488         59         14
   136510     138100         47       136425     139488         59         15
   136506     138114         53       136425     139488         59         16
   136510     138197         50       136425     139488         59         17
   136510     138240         47       136425     139488         59         18
   136506     138844         56       136425     139488         59         19
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   136510     138205         47       136425     139488         59         20
   136463     138306         59       136425     139488         61         21
   136504     137805         44       136425     139488         60         22
   136506     137562         43       136425     139488         60         23
   136506     137890         45       136425     139488         60         24
   136472     137660         44       136425     139488         60         25
   136484     138450         48       136425     139488         60         26
   136506     138160         48       136425     139488         60         27
   136510     138051         47       136425     139488         59         28
   136510     137688         40       136425     139488         59         29
   136468     138439         53       136425     139488         59         30
   136504     138450         54       136425     139488         59         31
   136445     138374         59       136425     139488         60         32
   136466     140111         74       136425     140111         62         33
   136512     137573         42       136425     140111         61         34
   136508     138335         49       136425     140111         61         35
   136468     137388         52       136425     140111         62         36
   136508     137867         48       136425     140111         61         37
   136465     138511         57       136425     140111         62         38
   136510     138704         50       136425     140111         61         39
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   136508     138045         56       136425     140111         62         40
   136508     137826         49       136425     140111         61         41
   136463     138623         55       136425     140111         62         42
   136508     138197         43       136425     140111         61         43
   136508     137826         49       136425     140111         61         44
   136506     139182         59       136425     140111         61         45
   136508     138138         45       136425     140111         61         46
   136500     138143         55       136425     140111         61         47
   136510     146543        108       136425     146543         63         48
   136470     138335         54       136425     146543         63         49
   136506     138018         51       136425     146543         63         50
   136510     138891         49       136425     146543         63         51
   136510     140170         56       136425     146543         63         52
   136512     137923         46       136425     146543         63         53
   136402     137903         56       136402     146543         63         54
   136508     138177         49       136402     146543         63         55
   136508     138571         52       136402     146543         62         56
   136466     137980         49       136402     146543         63         57
   136510     137450         43       136402     146543         62         58
   136464     137737         48       136402     146543         62         59
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   136508     138206         48       136402     146543         62         60
   136462     138777         65       136402     146543         63         61
   136506     138088         45       136402     146543         63         62
   136502     138289         49       136402     146543         63         63
   136507     138684         56       136402     146543         63         64
   136510     138270         53       136402     146543         63         65
   136508     138780         51       136402     146543         63         66
   136506     138076         49       136402     146543         62         67
   136504     138679         54       136402     146543         62         68
   136508     138272         50       136402     146543         62         69
   136475     138588         50       136402     146543         62         70
   136452     137486         42       136402     146543         62         71
   136510     138552         52       136402     146543         62         72
   136512     150494        148       136402     150494         64         73
   136463     138472         56       136402     150494         64         74
   136508     138250         50       136402     150494         64         75
   136506     137980         44       136402     150494         64         76
   136488     138295         52       136402     150494         64         77
   136508     138230         50       136402     150494         64         78
   136506     138383         52       136402     150494         64         79
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   136508     137846         46       136402     150494         64         80
   136510     138988         53       136402     150494         64         81
   136508     138917         57       136402     150494         64         82
   136508     137812         49       136402     150494         64         83
   136453     138747         64       136402     150494         64         84
   136506     137755         41       136402     150494         64         85
   136508     138071         51       136402     150494         64         86
   136463     138562         64       136402     150494         64         87
   136508     138082         48       136402     150494         64         88
   136508     138585         49       136402     150494         64         89
   136504     138204         44       136402     150494         64         90
   136508     138240         48       136402     150494         64         91
   136472     138176         51       136402     150494         64         92
   136504     137989         46       136402     150494         64         93
   136508     139037         51       136402     150494         64         94
   136451     138800         50       136402     150494         64         95
   136507     138291         53       136402     150494         64         96
   136421     138264         56       136402     150494         64         97
   136425     138072         48       136402     150494         65         98
   136427     137412         42       136402     150494         65         99
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   136419     138854         59       136402     150494         66        100
   136426     138813         53       136402     150494         66        101
   136404     138154         59       136402     150494         67        102
   136425     137848         49       136402     150494         68        103
   136366     137504         43       136366     150494         68        104
   136421     138570         54       136366     150494         69        105
   136425     138422         52       136366     150494         69        106
   136423     138471         50       136366     150494         69        107
   136420     138197         47       136366     150494         70        108
   136425     137538         44       136366     150494         70        109
   136420     138654         54       136366     150494         71        110
   136425     138980         58       136366     150494         71        111
   136419     137938         46       136366     150494         72        112
   136419     139523         50       136366     150494         72        113
   136421     138043         54       136366     150494         72        114
   136362     139377         72       136362     150494         73        115
   136423     138857         53       136362     150494         74        116
   136422     138532         48       136362     150494         74        117
   136423     138661         53       136362     150494         74        118
   136435     138433         56       136362     150494         75        119
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   136401     138061         55       136362     150494         75        120
   136425     137694         46       136362     150494         75        121
   136419     137913         47       136362     150494         76        122
   136421     138905         55       136362     150494         76        123
   136421     138522         50       136362     150494         76        124
   136423     138540         53       136362     150494         77        125
   136391     138374         59       136362     150494         77        126
   136429     138686         45       136362     150494         77        127
   136421     137781         54       136362     150494         78        128
   136418     138191         51       136362     150494         78        129
   136423     138306         50       136362     150494         78        130
   136427     137795         50       136362     150494         78        131
   136366     137817         44       136362     150494         79        132
   136423     138865         60       136362     150494         79        133
   136425     138064         50       136362     150494         79        134
   136386     137690         52       136362     150494         80        135
   136423     138749         56       136362     150494         80        136
   136405     138928         57       136362     150494         80        137
   136423     138769         60       136362     150494         80        138
   136427     138102         52       136362     150494         81        139
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   136421     138550         51       136362     150494         81        140
   136406     137283         52       136362     150494         81        141
   136427     138574         55       136362     150494         81        142
   136421     137561         45       136362     150494         82        143
   136425     138631         53       136362     150494         82        144
   136423     138418         56       136362     150494         82        145
   136431     138294         50       136362     150494         82        146
   136419     138443         60       136362     150494         82        147
   136427     138623         59       136362     150494         83        148
   136419     138917         51       136362     150494         83        149
   136423     139846         51       136362     150494         83        150
   136427     137885         52       136362     150494         83        151
   136424     138414         52       136362     150494         83        152
   136429     137703         44       136362     150494         84        153
   136424     137379         44       136362     150494         84        154
   136425     138459         47       136362     150494         84        155
   136423     139090         52       136362     150494         84        156
   136427     138532         54       136362     150494         84        157
   136400     137648         49       136362     150494         84        158
   136425     138348         52       136362     150494         85        159
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   136425     137824         46       136362     150494         85        160
   136405     138270         55       136362     150494         85        161
   136423     138418         54       136362     150494         85        162
   136425     138471         50       136362     150494         85        163
   136423     138309         47       136362     150494         85        164
   136422     138331         50       136362     150494         86        165
   136421     137916         58       136362     150494         86        166
   136419     137936         51       136362     150494         86        167
   136425     137968         49       136362     150494         86        168
   136419     137530         42       136362     150494         86        169
   136425     137848         48       136362     150494         86        170
   136425     138444         54       136362     150494         86        171
   136421     138009         47       136362     150494         86        172
   136364     139589         63       136362     150494         87        173
   136424     138126         46       136362     150494         87        174
   136390     138070         65       136362     150494         87        175
   136423     138421         57       136362     150494         87        176
   136429     137518         43       136362     150494         88        177
   136419     144453         91       136362     150494         88        178
   136422     137676         46       136362     150494         88        179
SampleMin  SampleMax   SmplJitter  SessionMin SessionMax SessionJitter  Sample
   136422     137723         46       136362     150494         88        180
   136397     137761         56       136362     150494         88        181
   136425     137944         50       136362     150494         88        182
   136425     137417         40       136362     150494         88        183
   136423     138460         61       136362     150494         89        184
   136421     139004         61       136362     150494         89        185
   136423     138311         46       136362     150494         89        186
   136420     138114         49       136362     150494         89        187
   136421     137773         46       136362     150494         89        188
   136419     138080         57       136362     150494         89        189
   136425     137572         47       136362     150494         89        190
   136403     137575         42       136362     150494         89        191
   136425     137707         41       136362     150494         89        192
   136423     139539         58       136362     150494         90        193
   136428     138286         53       136362     150494         90        194
   136425     138345         45       136362     150494         90        195
   136420     138542         57       136362     150494         90        196
   136423     138174         49       136362     150494         90        197
   136422     139306         64       136362     150494         90        198
   136419     139805         60       136362     150494         90        199

Latency Results

See also

See section Rhealstone for more information on this benchmark.

The following configuration was used:

• Core affinity = 1

• Noisy Neighbor stress-ng affinity = 2

• Test time = 10 seconds

• SSH session (not using integrated GPU)

Vecow Core i7-8665UE - Latency

Click to toggle results

#  Test case (1/9): Test.cobalt.latency.no_stress
#..............................................................................
#No stress requested
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.no_stress_histogram
#Hung task detection not supported
#  (File /proc/sys/kernel/hung_task_timeout_secs not found)
#23:07:28: Start of execution
#23:07:39:  1/ 1: min: 6.789 avg: 7.512 max: 10.312
#23:07:39: Test completed. Actual execution time:0:00:11
#Avg: 7.512 us
#Max: 10.312 us
#Max list: [10.312]
#PASS

Test.latency.no_stress[Avg/us, Max/us]:
7.512, 10.312
PASS:Test.latency.no_stress

#==============================================================================
#  Test case (2/9): Test.cobalt.latency.cpu
#..............................................................................
#Starting stress(cpu)
#  Command: 'taskset -c 0 stress -q -c 4'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.cpu_histogram
#23:07:39: Start of execution
#23:07:50:  1/ 1: min: 6.804 avg: 7.527 max: 11.925
#23:07:50: Test completed. Actual execution time:0:00:11
#Terminated stress
#Avg: 7.527 us
#Max: 11.925 us
#Max list: [11.925]
#PASS

Test.latency.cpu[Avg/us, Max/us]:
7.527, 11.925
PASS:Test.latency.cpu

#==============================================================================
#  Test case (3/9): Test.cobalt.latency.hdd
#..............................................................................
#Starting stress(hdd)
#  Command: 'taskset -c 0 stress -q -d 4 --hdd-bytes 20M'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.hdd_histogram
#23:07:50: Start of execution
#23:08:01:  1/ 1: min: 6.829 avg: 9.145 max: 53.068
#23:08:01: Test completed. Actual execution time:0:00:11
#Terminated stress
#Avg: 9.145 us
#Max: 53.068 us
#Max list: [53.068]
#PASS

Test.latency.hdd[Avg/us, Max/us]:
9.145, 53.068
PASS:Test.latency.hdd

#==============================================================================
#  Test case (4/9): Test.cobalt.latency.io
#..............................................................................
#Starting stress(io)
#  Command: 'taskset -c 0 stress -q -i 4'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.io_histogram
#23:08:01: Start of execution
#23:08:12:  1/ 1: min: 6.818 avg: 7.659 max: 9.851
#23:08:12: Test completed. Actual execution time:0:00:11
#Terminated stress
#Avg: 7.659 us
#Max: 9.851 us
#Max list: [9.851]
#PASS

Test.latency.io[Avg/us, Max/us]:
7.659, 9.851
PASS:Test.latency.io

#==============================================================================
#  Test case (5/9): Test.cobalt.latency.vm
#..............................................................................
#Starting stress(vm)
#  Command: 'taskset -c 0 stress -q -m 4 --vm-bytes 10M'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.vm_histogram
#23:08:12: Start of execution
#23:08:23:  1/ 1: min: 6.920 avg: 9.236 max: 32.678
#23:08:23: Test completed. Actual execution time:0:00:11
#Terminated stress
#Avg: 9.236 us
#Max: 32.678 us
#Max list: [32.678]
#PASS

Test.latency.vm[Avg/us, Max/us]:
9.236, 32.678
PASS:Test.latency.vm

#==============================================================================
#  Test case (6/9): Test.cobalt.latency.full
#..............................................................................
#Starting stress(io+cpu+hdd+vm)
#  Command: 'taskset -c 0 stress -q -i 4 -q -c 4 -q -d 4 --hdd-bytes 20M -q -m 4 --vm-bytes 10M'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.full_histogram
#23:08:23: Start of execution
#23:08:34:  1/ 1: min: 6.790 avg: 8.503 max: 59.032
#23:08:34: Test completed. Actual execution time:0:00:11
#Terminated stress
#Avg: 8.503 us
#Max: 59.032 us
#Max list: [59.032]
#PASS

Test.latency.full[Avg/us, Max/us]:
8.503, 59.032
PASS:Test.latency.full

#==============================================================================
#  Test case (7/9): Test.cobalt.latency.gfx
#..............................................................................
#Starting stress(gfx)
#  Command: 'taskset -c 0 glxgears'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.gfx_histogram
#23:08:34: Start of execution
#23:08:45:  1/ 1: min: 6.814 avg: 7.532 max: 13.549
#23:08:45: Test completed. Actual execution time:0:00:11
#Exception!
#Traceback:Traceback (most recent call last):
#  File "./run_xlatency.py", line 416, in run_test
#    end_stress(p)
#  File "./run_xlatency.py", line 200, in end_stress
#    raise TestFail("stress prematurely terminated.")
#TestFail: Test failure: (stress prematurely terminated.)
#WD: /opt/benchmarking/rhealstone
#FAIL

FAIL:Test.latency.gfx

#==============================================================================
#  Test case (8/9): Test.cobalt.latency.l2-cache
#..............................................................................
#Starting stress(l2-cache)
#  Command: 'taskset -c 0 stress-ng -C 10 --cache-level 2 --taskset 0 --aggressive -v --metrics-brief > stress-ng.log2 2>/dev/null'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.l2-cache_histogram
#23:08:45: Start of execution
#23:08:56:  1/ 1: min: 6.823 avg: 7.535 max: 11.177
#23:08:56: Test completed. Actual execution time:0:00:11
#Terminated stress
#Avg: 7.535 us
#Max: 11.177 us
#Max list: [11.177]
#PASS

Test.latency.l2-cache[Avg/us, Max/us]:
7.535, 11.177
PASS:Test.latency.l2-cache

#==============================================================================
#  Test case (9/9): Test.cobalt.latency.l3-cache
#..............................................................................
#Starting stress(l3-cache)
#  Command: 'taskset -c 0 stress-ng -C 10 --cache-level 3 --taskset 0 --aggressive -v --metrics-brief > stress-ng.log3 2>/dev/null'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.l3-cache_histogram
#23:08:56: Start of execution
#23:09:07:  1/ 1: min: 6.838 avg: 10.320 max: 56.670
#23:09:07: Test completed. Actual execution time:0:00:11
#Terminated stress
#Avg: 10.320 us
#Max: 56.670 us
#Max list: [56.67]
#PASS

Test.latency.l3-cache[Avg/us, Max/us]:
10.320, 56.670
PASS:Test.latency.l3-cache

Maxtang Core i7-8665U - Latency

Click to toggle results

#  Test case (1/9): Test.cobalt.latency.no_stress
#..............................................................................
#No stress requested
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.no_stress_histogram
#Hung task detection not supported
#  (File /proc/sys/kernel/hung_task_timeout_secs not found)
#20:10:46: Start of execution
#20:10:57:  1/ 1: min: 6.148 avg: 6.805 max: 8.595
#20:10:57: Test completed. Actual execution time:0:00:11
#Avg: 6.805 us
#Max: 8.595 us
#Max list: [8.595]
#PASS

Test.latency.no_stress[Avg/us, Max/us]:
6.805, 8.595
PASS:Test.latency.no_stress

#==============================================================================
#  Test case (2/9): Test.cobalt.latency.cpu
#..............................................................................
#Starting stress(cpu)
#  Command: 'taskset -c 0 stress -q -c 4'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.cpu_histogram
#20:10:57: Start of execution
#20:11:08:  1/ 1: min: 6.164 avg: 6.806 max: 8.758
#20:11:08: Test completed. Actual execution time:0:00:11
#Terminated stress
#Avg: 6.806 us
#Max: 8.758 us
#Max list: [8.758]
#PASS

Test.latency.cpu[Avg/us, Max/us]:
6.806, 8.758
PASS:Test.latency.cpu

#==============================================================================
#  Test case (3/9): Test.cobalt.latency.hdd
#..............................................................................
#Starting stress(hdd)
#  Command: 'taskset -c 0 stress -q -d 4 --hdd-bytes 20M'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.hdd_histogram
#20:11:08: Start of execution
#20:11:19:  1/ 1: min: 6.161 avg: 7.746 max: 22.764
#20:11:19: Test completed. Actual execution time:0:00:11
#Terminated stress
#Avg: 7.746 us
#Max: 22.764 us
#Max list: [22.764]
#PASS

Test.latency.hdd[Avg/us, Max/us]:
7.746, 22.764
PASS:Test.latency.hdd

#==============================================================================
#  Test case (4/9): Test.cobalt.latency.io
#..............................................................................
#Starting stress(io)
#  Command: 'taskset -c 0 stress -q -i 4'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.io_histogram
#20:11:19: Start of execution
#20:11:30:  1/ 1: min: 6.151 avg: 6.787 max: 8.625
#20:11:30: Test completed. Actual execution time:0:00:11
#Terminated stress
#Avg: 6.787 us
#Max: 8.625 us
#Max list: [8.625]
#PASS

Test.latency.io[Avg/us, Max/us]:
6.787, 8.625
PASS:Test.latency.io

#==============================================================================
#  Test case (5/9): Test.cobalt.latency.vm
#..............................................................................
#Starting stress(vm)
#  Command: 'taskset -c 0 stress -q -m 4 --vm-bytes 10M'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.vm_histogram
#20:11:30: Start of execution
#20:11:41:  1/ 1: min: 6.295 avg: 7.718 max: 21.562
#20:11:41: Test completed. Actual execution time:0:00:11
#Terminated stress
#Avg: 7.718 us
#Max: 21.562 us
#Max list: [21.562]
#PASS

Test.latency.vm[Avg/us, Max/us]:
7.718, 21.562
PASS:Test.latency.vm

#==============================================================================
#  Test case (6/9): Test.cobalt.latency.full
#..............................................................................
#Starting stress(io+cpu+hdd+vm)
#  Command: 'taskset -c 0 stress -q -i 4 -q -c 4 -q -d 4 --hdd-bytes 20M -q -m 4 --vm-bytes 10M'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.full_histogram
#20:11:41: Start of execution
#20:11:52:  1/ 1: min: 6.126 avg: 7.316 max: 21.886
#20:11:52: Test completed. Actual execution time:0:00:11
#Terminated stress
#Avg: 7.316 us
#Max: 21.886 us
#Max list: [21.886]
#PASS

Test.latency.full[Avg/us, Max/us]:
7.316, 21.886
PASS:Test.latency.full

#==============================================================================
#  Test case (7/9): Test.cobalt.latency.gfx
#..............................................................................
#Starting stress(gfx)
#  Command: 'taskset -c 0 glxgears'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.gfx_histogram
#20:11:52: Start of execution
#20:12:03:  1/ 1: min: 6.138 avg: 6.777 max: 8.742
#20:12:03: Test completed. Actual execution time:0:00:11
#Exception!
#Traceback:Traceback (most recent call last):
#  File "./run_xlatency.py", line 416, in run_test
#    end_stress(p)
#  File "./run_xlatency.py", line 200, in end_stress
#    raise TestFail("stress prematurely terminated.")
#TestFail: Test failure: (stress prematurely terminated.)
#WD: /opt/benchmarking/rhealstone
#FAIL

FAIL:Test.latency.gfx

#==============================================================================
#  Test case (8/9): Test.cobalt.latency.l2-cache
#..............................................................................
#Starting stress(l2-cache)
#  Command: 'taskset -c 0 stress-ng -C 10 --cache-level 2 --taskset 0 --aggressive -v --metrics-brief > stress-ng.log2 2>/dev/null'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.l2-cache_histogram
#20:12:03: Start of execution
#20:12:14:  1/ 1: min: 6.171 avg: 6.814 max: 8.819
#20:12:14: Test completed. Actual execution time:0:00:11
#Terminated stress
#Avg: 6.814 us
#Max: 8.819 us
#Max list: [8.819]
#PASS

Test.latency.l2-cache[Avg/us, Max/us]:
6.814, 8.819
PASS:Test.latency.l2-cache

#==============================================================================
#  Test case (9/9): Test.cobalt.latency.l3-cache
#..............................................................................
#Starting stress(l3-cache)
#  Command: 'taskset -c 0 stress-ng -C 10 --cache-level 3 --taskset 0 --aggressive -v --metrics-brief > stress-ng.log3 2>/dev/null'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.l3-cache_histogram
#20:12:14: Start of execution
#20:12:25:  1/ 1: min: 6.161 avg: 8.890 max: 30.774
#20:12:25: Test completed. Actual execution time:0:00:11
#Terminated stress
#Avg: 8.890 us
#Max: 30.774 us
#Max list: [30.774]
#PASS

Test.latency.l3-cache[Avg/us, Max/us]:
8.890, 30.774
PASS:Test.latency.l3-cache

Vecow Core i7-1185G7E - Latency

Click to toggle results

#  Test case (1/9): Test.cobalt.latency.no_stress
#..............................................................................
#No stress requested
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.no_stress_histogram
#Hung task detection not supported
#  (File /proc/sys/kernel/hung_task_timeout_secs not found)
#16:06:13: Start of execution
#16:06:24:  1/ 1: min: 4.031 avg: 4.227 max: 8.876
#16:06:24: Test completed. Actual execution time:0:00:11
#Avg: 4.227 us
#Max: 8.876 us
#Max list: [8.876]
#PASS

Test.latency.no_stress[Avg/us, Max/us]:
4.227, 8.876
PASS:Test.latency.no_stress

#==============================================================================
#  Test case (2/9): Test.cobalt.latency.cpu
#..............................................................................
#Starting stress(cpu)
#  Command: 'taskset -c 0 stress -q -c 4'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.cpu_histogram
#16:06:24: Start of execution
#16:06:35:  1/ 1: min: 4.061 avg: 4.267 max: 5.847
#16:06:35: Test completed. Actual execution time:0:00:11
#Terminated stress
#Avg: 4.267 us
#Max: 5.847 us
#Max list: [5.847]
#PASS

Test.latency.cpu[Avg/us, Max/us]:
4.267, 5.847
PASS:Test.latency.cpu

#==============================================================================
#  Test case (3/9): Test.cobalt.latency.hdd
#..............................................................................
#Starting stress(hdd)
#  Command: 'taskset -c 0 stress -q -d 4 --hdd-bytes 20M'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.hdd_histogram
#16:06:35: Start of execution
#16:06:46:  1/ 1: min: 3.845 avg: 6.258 max: 11.917
#16:06:46: Test completed. Actual execution time:0:00:11
#Terminated stress
#Avg: 6.258 us
#Max: 11.917 us
#Max list: [11.917]
#PASS

Test.latency.hdd[Avg/us, Max/us]:
6.258, 11.917
PASS:Test.latency.hdd

#==============================================================================
#  Test case (4/9): Test.cobalt.latency.io
#..............................................................................
#Starting stress(io)
#  Command: 'taskset -c 0 stress -q -i 4'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.io_histogram
#16:06:46: Start of execution
#16:06:57:  1/ 1: min: 3.908 avg: 4.147 max: 6.619
#16:06:57: Test completed. Actual execution time:0:00:11
#Terminated stress
#Avg: 4.147 us
#Max: 6.619 us
#Max list: [6.619]
#PASS

Test.latency.io[Avg/us, Max/us]:
4.147, 6.619
PASS:Test.latency.io

#==============================================================================
#  Test case (5/9): Test.cobalt.latency.vm
#..............................................................................
#Starting stress(vm)
#  Command: 'taskset -c 0 stress -q -m 4 --vm-bytes 10M'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.vm_histogram
#16:06:57: Start of execution
#16:07:08:  1/ 1: min: 4.051 avg: 6.420 max: 12.756
#16:07:08: Test completed. Actual execution time:0:00:11
#Terminated stress
#Avg: 6.420 us
#Max: 12.756 us
#Max list: [12.756]
#PASS

Test.latency.vm[Avg/us, Max/us]:
6.420, 12.756
PASS:Test.latency.vm

#==============================================================================
#  Test case (6/9): Test.cobalt.latency.full
#..............................................................................
#Starting stress(io+cpu+hdd+vm)
#  Command: 'taskset -c 0 stress -q -i 4 -q -c 4 -q -d 4 --hdd-bytes 20M -q -m 4 --vm-bytes 10M'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.full_histogram
#16:07:08: Start of execution
#16:07:19:  1/ 1: min: 3.957 avg: 5.759 max: 14.653
#16:07:19: Test completed. Actual execution time:0:00:11
#Terminated stress
#Avg: 5.759 us
#Max: 14.653 us
#Max list: [14.653]
#PASS

Test.latency.full[Avg/us, Max/us]:
5.759, 14.653
PASS:Test.latency.full

#==============================================================================
#  Test case (7/9): Test.cobalt.latency.gfx
#..............................................................................
#Starting stress(gfx)
#  Command: 'taskset -c 0 glxgears'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.gfx_histogram
#16:07:19: Start of execution
#16:07:30:  1/ 1: min: 3.990 avg: 4.193 max: 6.988
#16:07:30: Test completed. Actual execution time:0:00:11
#Exception!
#Traceback:Traceback (most recent call last):
#  File "./run_xlatency.py", line 416, in run_test
#    end_stress(p)
#  File "./run_xlatency.py", line 200, in end_stress
#    raise TestFail("stress prematurely terminated.")
#TestFail: Test failure: (stress prematurely terminated.)
#WD: /opt/benchmarking/rhealstone
#FAIL

FAIL:Test.latency.gfx

#==============================================================================
#  Test case (8/9): Test.cobalt.latency.l2-cache
#..............................................................................
#Starting stress(l2-cache)
#  Command: 'taskset -c 0 stress-ng -C 10 --cache-level 2 --taskset 0 --aggressive -v --metrics-brief > stress-ng.log2 2>/dev/null'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.l2-cache_histogram
#16:07:30: Start of execution
#16:07:41:  1/ 1: min: 4.008 avg: 4.628 max: 19.751
#16:07:41: Test completed. Actual execution time:0:00:11
#Terminated stress
#Avg: 4.628 us
#Max: 19.751 us
#Max list: [19.751]
#PASS

Test.latency.l2-cache[Avg/us, Max/us]:
4.628, 19.751
PASS:Test.latency.l2-cache

#==============================================================================
#  Test case (9/9): Test.cobalt.latency.l3-cache
#..............................................................................
#Starting stress(l3-cache)
#  Command: 'taskset -c 0 stress-ng -C 10 --cache-level 3 --taskset 0 --aggressive -v --metrics-brief > stress-ng.log3 2>/dev/null'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.l3-cache_histogram
#16:07:41: Start of execution
#16:07:52:  1/ 1: min: 4.016 avg: 12.576 max: 36.885
#16:07:52: Test completed. Actual execution time:0:00:11
#Terminated stress
#Avg: 12.576 us
#Max: 36.885 us
#Max list: [36.885]
#PASS

Test.latency.l3-cache[Avg/us, Max/us]:
12.576, 36.885
PASS:Test.latency.l3-cache

Karbon 700 Core i7-9700TE - Latency

Click to toggle results

#  Test case (1/9): Test.cobalt.latency.no_stress
#..............................................................................
#No stress requested
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.no_stress_histogram
#Hung task detection not supported
#  (File /proc/sys/kernel/hung_task_timeout_secs not found)
#16:41:04: Start of execution
#16:41:15:  1/ 1: min: 3.467 avg: 3.829 max: 5.048
#16:41:15: Test completed. Actual execution time:0:00:11
#Avg: 3.829 us
#Max: 5.048 us
#Max list: [5.048]
#PASS

Test.latency.no_stress[Avg/us, Max/us]:
3.829, 5.048
PASS:Test.latency.no_stress

#==============================================================================
#  Test case (2/9): Test.cobalt.latency.cpu
#..............................................................................
#Starting stress(cpu)
#  Command: 'taskset -c 0 stress -q -c 8'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.cpu_histogram
#16:41:15: Start of execution
#16:41:26:  1/ 1: min: 3.506 avg: 3.858 max: 4.860
#16:41:26: Test completed. Actual execution time:0:00:11
#Terminated stress
#Avg: 3.858 us
#Max: 4.860 us
#Max list: [4.86]
#PASS

Test.latency.cpu[Avg/us, Max/us]:
3.858, 4.860
PASS:Test.latency.cpu

#==============================================================================
#  Test case (3/9): Test.cobalt.latency.hdd
#..............................................................................
#Starting stress(hdd)
#  Command: 'taskset -c 0 stress -q -d 8 --hdd-bytes 20M'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.hdd_histogram
#16:41:26: Start of execution
#16:41:37:  1/ 1: min: 3.468 avg: 4.479 max: 12.356
#16:41:37: Test completed. Actual execution time:0:00:11
#Terminated stress
#Avg: 4.479 us
#Max: 12.356 us
#Max list: [12.356]
#PASS

Test.latency.hdd[Avg/us, Max/us]:
4.479, 12.356
PASS:Test.latency.hdd

#==============================================================================
#  Test case (4/9): Test.cobalt.latency.io
#..............................................................................
#Starting stress(io)
#  Command: 'taskset -c 0 stress -q -i 8'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.io_histogram
#16:41:37: Start of execution
#16:41:48:  1/ 1: min: 3.494 avg: 4.019 max: 5.101
#16:41:48: Test completed. Actual execution time:0:00:11
#Terminated stress
#Avg: 4.019 us
#Max: 5.101 us
#Max list: [5.101]
#PASS

Test.latency.io[Avg/us, Max/us]:
4.019, 5.101
PASS:Test.latency.io

#==============================================================================
#  Test case (5/9): Test.cobalt.latency.vm
#..............................................................................
#Starting stress(vm)
#  Command: 'taskset -c 0 stress -q -m 8 --vm-bytes 10M'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.vm_histogram
#16:41:48: Start of execution
#16:41:59:  1/ 1: min: 3.491 avg: 4.144 max: 9.322
#16:41:59: Test completed. Actual execution time:0:00:11
#Terminated stress
#Avg: 4.144 us
#Max: 9.322 us
#Max list: [9.322]
#PASS

Test.latency.vm[Avg/us, Max/us]:
4.144, 9.322
PASS:Test.latency.vm

#==============================================================================
#  Test case (6/9): Test.cobalt.latency.full
#..............................................................................
#Starting stress(io+cpu+hdd+vm)
#  Command: 'taskset -c 0 stress -q -i 8 -q -c 8 -q -d 8 --hdd-bytes 20M -q -m 8 --vm-bytes 10M'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.full_histogram
#16:41:59: Start of execution
#16:42:10:  1/ 1: min: 3.450 avg: 4.160 max: 12.308
#16:42:10: Test completed. Actual execution time:0:00:11
#Terminated stress
#Avg: 4.160 us
#Max: 12.308 us
#Max list: [12.308]
#PASS

Test.latency.full[Avg/us, Max/us]:
4.160, 12.308
PASS:Test.latency.full

#==============================================================================
#  Test case (7/9): Test.cobalt.latency.gfx
#..............................................................................
#Starting stress(gfx)
#  Command: 'taskset -c 0 glxgears'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.gfx_histogram
#16:42:10: Start of execution
#16:42:21:  1/ 1: min: 3.480 avg: 3.830 max: 5.153
#16:42:21: Test completed. Actual execution time:0:00:11
#Exception!
#Traceback:Traceback (most recent call last):
#  File "./run_xlatency.py", line 416, in run_test
#    end_stress(p)
#  File "./run_xlatency.py", line 200, in end_stress
#    raise TestFail("stress prematurely terminated.")
#TestFail: Test failure: (stress prematurely terminated.)
#WD: /opt/benchmarking/rhealstone
#FAIL

FAIL:Test.latency.gfx

#==============================================================================
#  Test case (8/9): Test.cobalt.latency.l2-cache
#..............................................................................
#Starting stress(l2-cache)
#  Command: 'taskset -c 0 stress-ng -C 10 --cache-level 2 --taskset 0 --aggressive -v --metrics-brief > stress-ng.log2 2>/dev/null'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.l2-cache_histogram
#16:42:21: Start of execution
#16:42:32:  1/ 1: min: 3.433 avg: 3.816 max: 5.826
#16:42:32: Test completed. Actual execution time:0:00:11
#Terminated stress
#Avg: 3.816 us
#Max: 5.826 us
#Max list: [5.826]
#PASS

Test.latency.l2-cache[Avg/us, Max/us]:
3.816, 5.826
PASS:Test.latency.l2-cache

#==============================================================================
#  Test case (9/9): Test.cobalt.latency.l3-cache
#..............................................................................
#Starting stress(l3-cache)
#  Command: 'taskset -c 0 stress-ng -C 10 --cache-level 3 --taskset 0 --aggressive -v --metrics-brief > stress-ng.log3 2>/dev/null'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.l3-cache_histogram
#16:42:32: Start of execution
#16:42:43:  1/ 1: min: 3.458 avg: 5.249 max: 20.475
#16:42:43: Test completed. Actual execution time:0:00:11
#Terminated stress
#Avg: 5.249 us
#Max: 20.475 us
#Max list: [20.475]
#PASS

Test.latency.l3-cache[Avg/us, Max/us]:
5.249, 20.475
PASS:Test.latency.l3-cache

TGL-RVP Core i7-1185GRE - Latency

Click to toggle results

#  Test case (1/9): Test.cobalt.latency.no_stress
#..............................................................................
#No stress requested
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.no_stress_histogram
#Hung task detection not supported
#  (File /proc/sys/kernel/hung_task_timeout_secs not found)
#16:26:14: Start of execution
#16:26:25:  1/ 1: min: 3.935 avg: 4.105 max: 8.880
#16:26:25: Test completed. Actual execution time:0:00:11
#Avg: 4.105 us
#Max: 8.880 us
#Max list: [8.88]
#PASS

Test.latency.no_stress[Avg/us, Max/us]:
4.105, 8.880
PASS:Test.latency.no_stress

#==============================================================================
#  Test case (2/9): Test.cobalt.latency.cpu
#..............................................................................
#Starting stress(cpu)
#  Command: 'taskset -c 0 stress -q -c 4'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.cpu_histogram
#16:26:25: Start of execution
#16:26:36:  1/ 1: min: 3.947 avg: 4.117 max: 8.977
#16:26:36: Test completed. Actual execution time:0:00:11
#Terminated stress
#Avg: 4.117 us
#Max: 8.977 us
#Max list: [8.977]
#PASS

Test.latency.cpu[Avg/us, Max/us]:
4.117, 8.977
PASS:Test.latency.cpu

#==============================================================================
#  Test case (3/9): Test.cobalt.latency.hdd
#..............................................................................
#Starting stress(hdd)
#  Command: 'taskset -c 0 stress -q -d 4 --hdd-bytes 20M'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.hdd_histogram
#16:26:36: Start of execution
#16:26:47:  1/ 1: min: 4.159 avg: 6.458 max: 13.655
#16:26:47: Test completed. Actual execution time:0:00:11
#Terminated stress
#Avg: 6.458 us
#Max: 13.655 us
#Max list: [13.655]
#PASS

Test.latency.hdd[Avg/us, Max/us]:
6.458, 13.655
PASS:Test.latency.hdd

#==============================================================================
#  Test case (4/9): Test.cobalt.latency.io
#..............................................................................
#Starting stress(io)
#  Command: 'taskset -c 0 stress -q -i 4'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.io_histogram
#16:26:47: Start of execution
#16:26:58:  1/ 1: min: 4.162 avg: 4.378 max: 6.732
#16:26:58: Test completed. Actual execution time:0:00:11
#Terminated stress
#Avg: 4.378 us
#Max: 6.732 us
#Max list: [6.732]
#PASS

Test.latency.io[Avg/us, Max/us]:
4.378, 6.732
PASS:Test.latency.io

#==============================================================================
#  Test case (5/9): Test.cobalt.latency.vm
#..............................................................................
#Starting stress(vm)
#  Command: 'taskset -c 0 stress -q -m 4 --vm-bytes 10M'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.vm_histogram
#16:26:58: Start of execution
#16:27:09:  1/ 1: min: 4.606 avg: 5.909 max: 10.428
#16:27:09: Test completed. Actual execution time:0:00:11
#Terminated stress
#Avg: 5.909 us
#Max: 10.428 us
#Max list: [10.428]
#PASS

Test.latency.vm[Avg/us, Max/us]:
5.909, 10.428
PASS:Test.latency.vm

#==============================================================================
#  Test case (6/9): Test.cobalt.latency.full
#..............................................................................
#Starting stress(io+cpu+hdd+vm)
#  Command: 'taskset -c 0 stress -q -i 4 -q -c 4 -q -d 4 --hdd-bytes 20M -q -m 4 --vm-bytes 10M'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.full_histogram
#16:27:09: Start of execution
#16:27:20:  1/ 1: min: 4.022 avg: 5.571 max: 14.789
#16:27:20: Test completed. Actual execution time:0:00:11
#Terminated stress
#Avg: 5.571 us
#Max: 14.789 us
#Max list: [14.789]
#PASS

Test.latency.full[Avg/us, Max/us]:
5.571, 14.789
PASS:Test.latency.full

#==============================================================================
#  Test case (7/9): Test.cobalt.latency.gfx
#..............................................................................
#Starting stress(gfx)
#  Command: 'taskset -c 0 glxgears'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.gfx_histogram
#16:27:20: Start of execution
#16:27:31:  1/ 1: min: 4.010 avg: 4.193 max: 9.641
#16:27:31: Test completed. Actual execution time:0:00:11
#Exception!
#Traceback:Traceback (most recent call last):
#  File "./run_xlatency.py", line 416, in run_test
#    end_stress(p)
#  File "./run_xlatency.py", line 200, in end_stress
#    raise TestFail("stress prematurely terminated.")
#TestFail: Test failure: (stress prematurely terminated.)
#WD: /opt/benchmarking/rhealstone
#FAIL

FAIL:Test.latency.gfx

#==============================================================================
#  Test case (8/9): Test.cobalt.latency.l2-cache
#..............................................................................
#Starting stress(l2-cache)
#  Command: 'taskset -c 0 stress-ng -C 10 --cache-level 2 --taskset 0 --aggressive -v --metrics-brief > stress-ng.log2 2>/dev/null'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.l2-cache_histogram
#16:27:31: Start of execution
#16:27:42:  1/ 1: min: 3.961 avg: 4.577 max: 12.508
#16:27:42: Test completed. Actual execution time:0:00:11
#Terminated stress
#Avg: 4.577 us
#Max: 12.508 us
#Max list: [12.508]
#PASS

Test.latency.l2-cache[Avg/us, Max/us]:
4.577, 12.508
PASS:Test.latency.l2-cache

#==============================================================================
#  Test case (9/9): Test.cobalt.latency.l3-cache
#..............................................................................
#Starting stress(l3-cache)
#  Command: 'taskset -c 0 stress-ng -C 10 --cache-level 3 --taskset 0 --aggressive -v --metrics-brief > stress-ng.log3 2>/dev/null'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.l3-cache_histogram
#16:27:42: Start of execution
#16:27:53:  1/ 1: min: 4.017 avg: 11.705 max: 26.816
#16:27:53: Test completed. Actual execution time:0:00:11
#Terminated stress
#Avg: 11.705 us
#Max: 26.816 us
#Max list: [26.816]
#PASS

Test.latency.l3-cache[Avg/us, Max/us]:
11.705, 26.816
PASS:Test.latency.l3-cache

EHL-CRB Atom x6425RE - Latency

Click to toggle results

#  Test case (1/9): Test.cobalt.latency.no_stress
#..............................................................................
#No stress requested
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.no_stress_histogram
#Hung task detection not supported
#  (File /proc/sys/kernel/hung_task_timeout_secs not found)
#19:01:33: Start of execution
#19:01:44:  1/ 1: min: 7.424 avg: 7.736 max: 15.887
#19:01:44: Test completed. Actual execution time:0:00:11
#Avg: 7.736 us
#Max: 15.887 us
#Max list: [15.887]
#PASS

Test.latency.no_stress[Avg/us, Max/us]:
7.736, 15.887
PASS:Test.latency.no_stress

#==============================================================================
#  Test case (2/9): Test.cobalt.latency.cpu
#..............................................................................
#Starting stress(cpu)
#  Command: 'taskset -c 0 stress -q -c 4'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.cpu_histogram
#19:01:44: Start of execution
#19:01:55:  1/ 1: min: 7.399 avg: 7.787 max: 14.643
#19:01:55: Test completed. Actual execution time:0:00:11
#Terminated stress
#Avg: 7.787 us
#Max: 14.643 us
#Max list: [14.643]
#PASS

Test.latency.cpu[Avg/us, Max/us]:
7.787, 14.643
PASS:Test.latency.cpu

#==============================================================================
#  Test case (3/9): Test.cobalt.latency.hdd
#..............................................................................
#Starting stress(hdd)
#  Command: 'taskset -c 0 stress -q -d 4 --hdd-bytes 20M'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.hdd_histogram
#19:01:55: Start of execution
#19:02:06:  1/ 1: min: 7.751 avg: 11.909 max: 17.921
#19:02:06: Test completed. Actual execution time:0:00:11
#Terminated stress
#Avg: 11.909 us
#Max: 17.921 us
#Max list: [17.921]
#PASS

Test.latency.hdd[Avg/us, Max/us]:
11.909, 17.921
PASS:Test.latency.hdd

#==============================================================================
#  Test case (4/9): Test.cobalt.latency.io
#..............................................................................
#Starting stress(io)
#  Command: 'taskset -c 0 stress -q -i 4'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.io_histogram
#19:02:06: Start of execution
#19:02:17:  1/ 1: min: 7.644 avg: 8.158 max: 10.679
#19:02:17: Test completed. Actual execution time:0:00:11
#Terminated stress
#Avg: 8.158 us
#Max: 10.679 us
#Max list: [10.679]
#PASS

Test.latency.io[Avg/us, Max/us]:
8.158, 10.679
PASS:Test.latency.io

#==============================================================================
#  Test case (5/9): Test.cobalt.latency.vm
#..............................................................................
#Starting stress(vm)
#  Command: 'taskset -c 0 stress -q -m 4 --vm-bytes 10M'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.vm_histogram
#19:02:17: Start of execution
#19:02:28:  1/ 1: min: 9.717 avg: 12.189 max: 19.225
#19:02:28: Test completed. Actual execution time:0:00:11
#Terminated stress
#Avg: 12.189 us
#Max: 19.225 us
#Max list: [19.225]
#PASS

Test.latency.vm[Avg/us, Max/us]:
12.189, 19.225
PASS:Test.latency.vm

#==============================================================================
#  Test case (6/9): Test.cobalt.latency.full
#..............................................................................
#Starting stress(io+cpu+hdd+vm)
#  Command: 'taskset -c 0 stress -q -i 4 -q -c 4 -q -d 4 --hdd-bytes 20M -q -m 4 --vm-bytes 10M'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.full_histogram
#19:02:28: Start of execution
#19:02:39:  1/ 1: min: 7.714 avg: 10.508 max: 18.264
#19:02:39: Test completed. Actual execution time:0:00:11
#Terminated stress
#Avg: 10.508 us
#Max: 18.264 us
#Max list: [18.264]
#PASS

Test.latency.full[Avg/us, Max/us]:
10.508, 18.264
PASS:Test.latency.full

#==============================================================================
#  Test case (7/9): Test.cobalt.latency.gfx
#..............................................................................
#Starting stress(gfx)
#  Command: 'taskset -c 0 glxgears'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.gfx_histogram
#19:02:39: Start of execution
#19:02:50:  1/ 1: min: 7.773 avg: 8.104 max: 20.849
#19:02:50: Test completed. Actual execution time:0:00:11
#Exception!
#Traceback:Traceback (most recent call last):
#  File "./run_xlatency.py", line 416, in run_test
#    end_stress(p)
#  File "./run_xlatency.py", line 200, in end_stress
#    raise TestFail("stress prematurely terminated.")
#TestFail: Test failure: (stress prematurely terminated.)
#WD: /opt/benchmarking/rhealstone
#FAIL

FAIL:Test.latency.gfx

#==============================================================================
#  Test case (8/9): Test.cobalt.latency.l2-cache
#..............................................................................
#Starting stress(l2-cache)
#  Command: 'taskset -c 0 stress-ng -C 10 --cache-level 2 --taskset 0 --aggressive -v --metrics-brief > stress-ng.log2 2>/dev/null'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.l2-cache_histogram
#19:02:50: Start of execution
#19:03:01:  1/ 1: min: 8.017 avg: 10.634 max: 19.227
#19:03:01: Test completed. Actual execution time:0:00:11
#Terminated stress
#Avg: 10.634 us
#Max: 19.227 us
#Max list: [19.227]
#PASS

Test.latency.l2-cache[Avg/us, Max/us]:
10.634, 19.227
PASS:Test.latency.l2-cache

#==============================================================================
#  Test case (9/9): Test.cobalt.latency.l3-cache
#..............................................................................
#Starting stress(l3-cache)
#  Command: 'taskset -c 0 stress-ng -C 10 --cache-level 3 --taskset 0 --aggressive -v --metrics-brief > stress-ng.log3 2>/dev/null'
#Starting test
#  Command: taskset -c 1 ./latency -p 250 -T 10 -c 1 -s -g Test.latency.l3-cache_histogram
#19:03:01: Start of execution
#19:03:12:  1/ 1: min: 10.477 avg: 19.248 max: 27.432
#19:03:12: Test completed. Actual execution time:0:00:11
#Terminated stress
#Avg: 19.248 us
#Max: 27.432 us
#Max list: [27.432]
#PASS

Test.latency.l3-cache[Avg/us, Max/us]:
19.248, 27.432
PASS:Test.latency.l3-cache

MSI Latency Results

See also

See section MSI Latency for more information on this benchmark.

The following configuration was used:

• coreSpecIRQ = 1

• coreSpecWQ = 1

• irqSpec = 1

• irqPeriod = 10

• irqCount = 2000000

• verbosity = 1

• offsetStart = 0

• blockIRQ = 0

Vecow Core i7-8665UE - MSI Latency

Click to toggle results

TBD

Maxtang Core i7-8665U - MSI Latency

Click to toggle results

TBD

Vecow Core i7-1185G7E - MSI Latency

Click to toggle results

TBD

Karbon 700 Core i7-9700TE - MSI Latency

Click to toggle results

TBD

TGL-RVP Core i7-1185GRE - MSI Latency

Click to toggle results

TBD

MSI Jitter Results

See also

See section MSI Jitter for more information about this benchmark.

The following configuration was used:

• core affinity = 1

• runtime = 10(s)

• interval = 10(ms)

• unbind_igb_id (checked by lspci)

Vecow Core i7-8665UE - MSI Jitter

Click to toggle results

************ RESULTS (ns) ************
   [ 1584.838928] * Max: 4624
   [ 1584.838929] * Avg: 298
   [ 1584.838929] * Min: 0

Maxtang Core i7-8665U - MSI Jitter

Click to toggle results

************ RESULTS (ns) ************

   [  974.372924] * Max: 896
   [  974.372924] * Avg: 131
   [  974.372925] * Min: 0

Vecow Core i7-1185G7E - MSI Jitter

Click to toggle results

TBD

Karbon 700 Core i7-9700TE - MSI Jitter

Click to toggle results

TBD

TGL-RVP Core i7-1185GRE - MSI Jitter

Click to toggle results

TBD

EHL-CRB ATOM x6425RE - MSI Jitter

Click to toggle results

TBD

Rhealstone Results

See also

See section Rhealstone for more information about this benchmark.

The following configuration was used:

• Core affinity = 1

• Total loops = 1

• Noisy Neighbor stress-ng affinity = 2

• SSH session (not using integrated GPU)

Vecow Core i7-8665UE - Rhealstone

Click to toggle results

#node: ecs-intel-6102
#release: 5.4.115-rt57-intel-pk-preempt-rt
#version: #1 SMP PREEMPT_RT Thu May 6 14:42:12 UTC 2021
#machine: x86_64
#processor: x86_64
#    0:  Intel(R) Core(TM) i7-8665UE CPU @ 1.70GHz
#    1:  Intel(R) Core(TM) i7-8665UE CPU @ 1.70GHz
#    2:  Intel(R) Core(TM) i7-8665UE CPU @ 1.70GHz
#    3:  Intel(R) Core(TM) i7-8665UE CPU @ 1.70GHz
#==============================================================================
#  Test start add stress
#  Test case (1/24): ino_bmark.ctx_msg_posix.no_stress
#..............................................................................
#No stress requested
#
#[1212.91]
#ctx_sum is 1212.91
#ctx_avg is 1212.91
#
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (2/24): ino_bmark.ctx_msg_posix.cpu
#..............................................................................
#Starting stress(cpu)
#  Command: 'taskset -c 0 stress-ng -q -c 4'
#
#[1199.48]
#ctx_sum is 1199.48
#ctx_avg is 1199.48
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (3/24): ino_bmark.ctx_msg_posix.hdd
#..............................................................................
#Starting stress(hdd)
#  Command: 'taskset -c 0 stress-ng -q -d 4 --hdd-bytes 20M'
#
#[1260.38]
#ctx_sum is 1260.38
#ctx_avg is 1260.38
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (4/24): ino_bmark.ctx_msg_posix.io
#..............................................................................
#Starting stress(io)
#  Command: 'taskset -c 0 stress-ng -q -i 4'
#
#[1200.16]
#ctx_sum is 1200.16
#ctx_avg is 1200.16
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (5/24): ino_bmark.ctx_msg_posix.vm
#..............................................................................
#Starting stress(vm)
#  Command: 'taskset -c 0 stress-ng -q -m 4 --vm-bytes 10M'
#
#[1214.03]
#ctx_sum is 1214.03
#ctx_avg is 1214.03
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (6/24): ino_bmark.ctx_msg_posix.full
#..............................................................................
#Starting stress(io+cpu+hdd+vm)
#  Command: 'taskset -c 0 stress-ng -q -i 4 -c 4 -d 4 --hdd-bytes 20M -m 4 --vm-bytes 10M'
#
#[1230.14]
#ctx_sum is 1230.14
#ctx_avg is 1230.14
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (7/24): ino_bmark.deadlock_posix.no_stress
#..............................................................................
#No stress requested
#
#[6080.78]
#dead_sum is 6080.780000
#dead_avg is 6080.780000
#
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (8/24): ino_bmark.deadlock_posix.cpu
#..............................................................................
#Starting stress(cpu)
#  Command: 'taskset -c 0 stress-ng -q -c 4'
#
#[6315.0]
#dead_sum is 6315.000000
#dead_avg is 6315.000000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (9/24): ino_bmark.deadlock_posix.hdd
#..............................................................................
#Starting stress(hdd)
#  Command: 'taskset -c 0 stress-ng -q -d 4 --hdd-bytes 20M'
#
#[6032.366667]
#dead_sum is 6032.366667
#dead_avg is 6032.366667
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (10/24): ino_bmark.deadlock_posix.io
#..............................................................................
#Starting stress(io)
#  Command: 'taskset -c 0 stress-ng -q -i 4'
#
#[6248.043333]
#dead_sum is 6248.043333
#dead_avg is 6248.043333
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (11/24): ino_bmark.deadlock_posix.vm
#..............................................................................
#Starting stress(vm)
#  Command: 'taskset -c 0 stress-ng -q -m 4 --vm-bytes 10M'
#
#[6238.473333]
#dead_sum is 6238.473333
#dead_avg is 6238.473333
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (12/24): ino_bmark.deadlock_posix.full
#..............................................................................
#Starting stress(io+cpu+hdd+vm)
#  Command: 'taskset -c 0 stress-ng -q -i 4 -c 4 -d 4 --hdd-bytes 20M -m 4 --vm-bytes 10M'
#
#[6248.633333]
#dead_sum is 6248.633333
#dead_avg is 6248.633333
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (13/24): ino_bmark.preempt_posix.no_stress
#..............................................................................
#No stress requested
#
#[5642.53]
#pree_sum is 5642.530000
#pree_avg is 5642.530000
#
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (14/24): ino_bmark.preempt_posix.cpu
#..............................................................................
#Starting stress(cpu)
#  Command: 'taskset -c 0 stress-ng -q -c 4'
#
#[5577.13]
#pree_sum is 5577.130000
#pree_avg is 5577.130000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (15/24): ino_bmark.preempt_posix.hdd
#..............................................................................
#Starting stress(hdd)
#  Command: 'taskset -c 0 stress-ng -q -d 4 --hdd-bytes 20M'
#
#[5587.225]
#pree_sum is 5587.225000
#pree_avg is 5587.225000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (16/24): ino_bmark.preempt_posix.io
#..............................................................................
#Starting stress(io)
#  Command: 'taskset -c 0 stress-ng -q -i 4'
#
#[5584.19]
#pree_sum is 5584.190000
#pree_avg is 5584.190000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (17/24): ino_bmark.preempt_posix.vm
#..............................................................................
#Starting stress(vm)
#  Command: 'taskset -c 0 stress-ng -q -m 4 --vm-bytes 10M'
#
#[5648.065]
#pree_sum is 5648.065000
#pree_avg is 5648.065000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (18/24): ino_bmark.preempt_posix.full
#..............................................................................
#Starting stress(io+cpu+hdd+vm)
#  Command: 'taskset -c 0 stress-ng -q -i 4 -c 4 -d 4 --hdd-bytes 20M -m 4 --vm-bytes 10M'
#
#[5643.115]
#pree_sum is 5643.115000
#pree_avg is 5643.115000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (19/24): ino_bmark.semaphore_posix.no_stress
#..............................................................................
#No stress requested
#
#[3552.925]
#sem_sum is 3552.925000
#sem_avg is 3552.925000
#
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (20/24): ino_bmark.semaphore_posix.cpu
#..............................................................................
#Starting stress(cpu)
#  Command: 'taskset -c 0 stress-ng -q -c 4'
#
#[3454.085]
#sem_sum is 3454.085000
#sem_avg is 3454.085000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (21/24): ino_bmark.semaphore_posix.hdd
#..............................................................................
#Starting stress(hdd)
#  Command: 'taskset -c 0 stress-ng -q -d 4 --hdd-bytes 20M'
#
#[4075.935]
#sem_sum is 4075.935000
#sem_avg is 4075.935000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (22/24): ino_bmark.semaphore_posix.io
#..............................................................................
#Starting stress(io)
#  Command: 'taskset -c 0 stress-ng -q -i 4'
#
#[3521.81]
#sem_sum is 3521.810000
#sem_avg is 3521.810000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (23/24): ino_bmark.semaphore_posix.vm
#..............................................................................
#Starting stress(vm)
#  Command: 'taskset -c 0 stress-ng -q -m 4 --vm-bytes 10M'
#
#[3718.345]
#sem_sum is 3718.345000
#sem_avg is 3718.345000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (24/24): ino_bmark.semaphore_posix.full
#..............................................................................
#Starting stress(io+cpu+hdd+vm)
#  Command: 'taskset -c 0 stress-ng -q -i 4 -c 4 -d 4 --hdd-bytes 20M -m 4 --vm-bytes 10M'
#
#[4222.265]
#sem_sum is 4222.265000
#sem_avg is 4222.265000
#
#Terminated stress
#Test End

Maxtang Core i7-8665U - Rhealstone

Click to toggle results

#node: ecs-intel-58bd
#release: 5.4.66-intel-pk-standard
#version: #1 SMP PREEMPT Fri Sep 25 01:54:34 UTC 2020
#machine: x86_64
#processor: x86_64
#    0:  Intel(R) Core(TM) i7-8665U CPU @ 1.90GHz
#    1:  Intel(R) Core(TM) i7-8665U CPU @ 1.90GHz
#    2:  Intel(R) Core(TM) i7-8665U CPU @ 1.90GHz
#    3:  Intel(R) Core(TM) i7-8665U CPU @ 1.90GHz
#==============================================================================
#  Test start add stress
#  Test case (1/24): ino_bmark.ctx_msg_posix.no_stress
#..............................................................................
#No stress requested
#
#[838.87]
#ctx_sum is 838.87
#ctx_avg is 838.87
#
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (2/24): ino_bmark.ctx_msg_posix.cpu
#..............................................................................
#Starting stress(cpu)
#  Command: 'taskset -c 0 stress-ng -q -c 4'
#
#[821.85]
#ctx_sum is 821.85
#ctx_avg is 821.85
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (3/24): ino_bmark.ctx_msg_posix.hdd
#..............................................................................
#Starting stress(hdd)
#  Command: 'taskset -c 0 stress-ng -q -d 4 --hdd-bytes 20M'
#
#[815.8]
#ctx_sum is 815.80
#ctx_avg is 815.80
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (4/24): ino_bmark.ctx_msg_posix.io
#..............................................................................
#Starting stress(io)
#  Command: 'taskset -c 0 stress-ng -q -i 4'
#
#[843.7]
#ctx_sum is 843.70
#ctx_avg is 843.70
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (5/24): ino_bmark.ctx_msg_posix.vm
#..............................................................................
#Starting stress(vm)
#  Command: 'taskset -c 0 stress-ng -q -m 4 --vm-bytes 10M'
#
#[817.26]
#ctx_sum is 817.26
#ctx_avg is 817.26
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (6/24): ino_bmark.ctx_msg_posix.full
#..............................................................................
#Starting stress(io+cpu+hdd+vm)
#  Command: 'taskset -c 0 stress-ng -q -i 4 -c 4 -d 4 --hdd-bytes 20M -m 4 --vm-bytes 10M'
#
#[828.18]
#ctx_sum is 828.18
#ctx_avg is 828.18
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (7/24): ino_bmark.deadlock_posix.no_stress
#..............................................................................
#No stress requested
#
#[2174.043333]
#dead_sum is 2174.043333
#dead_avg is 2174.043333
#
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (8/24): ino_bmark.deadlock_posix.cpu
#..............................................................................
#Starting stress(cpu)
#  Command: 'taskset -c 0 stress-ng -q -c 4'
#
#[2188.863333]
#dead_sum is 2188.863333
#dead_avg is 2188.863333
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (9/24): ino_bmark.deadlock_posix.hdd
#..............................................................................
#Starting stress(hdd)
#  Command: 'taskset -c 0 stress-ng -q -d 4 --hdd-bytes 20M'
#
#[2189.91]
#dead_sum is 2189.910000
#dead_avg is 2189.910000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (10/24): ino_bmark.deadlock_posix.io
#..............................................................................
#Starting stress(io)
#  Command: 'taskset -c 0 stress-ng -q -i 4'
#
#[2159.3]
#dead_sum is 2159.300000
#dead_avg is 2159.300000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (11/24): ino_bmark.deadlock_posix.vm
#..............................................................................
#Starting stress(vm)
#  Command: 'taskset -c 0 stress-ng -q -m 4 --vm-bytes 10M'
#
#[2148.9]
#dead_sum is 2148.900000
#dead_avg is 2148.900000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (12/24): ino_bmark.deadlock_posix.full
#..............................................................................
#Starting stress(io+cpu+hdd+vm)
#  Command: 'taskset -c 0 stress-ng -q -i 4 -c 4 -d 4 --hdd-bytes 20M -m 4 --vm-bytes 10M'
#
#[2200.24]
#dead_sum is 2200.240000
#dead_avg is 2200.240000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (13/24): ino_bmark.preempt_posix.no_stress
#..............................................................................
#No stress requested
#
#[633.805]
#pree_sum is 633.805000
#pree_avg is 633.805000
#
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (14/24): ino_bmark.preempt_posix.cpu
#..............................................................................
#Starting stress(cpu)
#  Command: 'taskset -c 0 stress-ng -q -c 4'
#
#[631.185]
#pree_sum is 631.185000
#pree_avg is 631.185000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (15/24): ino_bmark.preempt_posix.hdd
#..............................................................................
#Starting stress(hdd)
#  Command: 'taskset -c 0 stress-ng -q -d 4 --hdd-bytes 20M'
#
#[648.05]
#pree_sum is 648.050000
#pree_avg is 648.050000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (16/24): ino_bmark.preempt_posix.io
#..............................................................................
#Starting stress(io)
#  Command: 'taskset -c 0 stress-ng -q -i 4'
#
#[640.12]
#pree_sum is 640.120000
#pree_avg is 640.120000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (17/24): ino_bmark.preempt_posix.vm
#..............................................................................
#Starting stress(vm)
#  Command: 'taskset -c 0 stress-ng -q -m 4 --vm-bytes 10M'
#
#[644.315]
#pree_sum is 644.315000
#pree_avg is 644.315000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (18/24): ino_bmark.preempt_posix.full
#..............................................................................
#Starting stress(io+cpu+hdd+vm)
#  Command: 'taskset -c 0 stress-ng -q -i 4 -c 4 -d 4 --hdd-bytes 20M -m 4 --vm-bytes 10M'
#
#[656.09]
#pree_sum is 656.090000
#pree_avg is 656.090000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (19/24): ino_bmark.semaphore_posix.no_stress
#..............................................................................
#No stress requested
#
#[2005.32]
#sem_sum is 2005.320000
#sem_avg is 2005.320000
#
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (20/24): ino_bmark.semaphore_posix.cpu
#..............................................................................
#Starting stress(cpu)
#  Command: 'taskset -c 0 stress-ng -q -c 4'
#
#[2051.645]
#sem_sum is 2051.645000
#sem_avg is 2051.645000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (21/24): ino_bmark.semaphore_posix.hdd
#..............................................................................
#Starting stress(hdd)
#  Command: 'taskset -c 0 stress-ng -q -d 4 --hdd-bytes 20M'
#
#[2063.165]
#sem_sum is 2063.165000
#sem_avg is 2063.165000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (22/24): ino_bmark.semaphore_posix.io
#..............................................................................
#Starting stress(io)
#  Command: 'taskset -c 0 stress-ng -q -i 4'
#
#[2010.165]
#sem_sum is 2010.165000
#sem_avg is 2010.165000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (23/24): ino_bmark.semaphore_posix.vm
#..............................................................................
#Starting stress(vm)
#  Command: 'taskset -c 0 stress-ng -q -m 4 --vm-bytes 10M'
#
#[2036.26]
#sem_sum is 2036.260000
#sem_avg is 2036.260000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (24/24): ino_bmark.semaphore_posix.full
#..............................................................................
#Starting stress(io+cpu+hdd+vm)
#  Command: 'taskset -c 0 stress-ng -q -i 4 -c 4 -d 4 --hdd-bytes 20M -m 4 --vm-bytes 10M'
#
#[2030.2]
#sem_sum is 2030.200000
#sem_avg is 2030.200000
#
#Terminated stress
#Test End

Vecow Core i7-1185G7E - Rhealstone

Click to toggle results

#node: ecs-intel-ebfb
#release: 5.4.115-rt57-intel-pk-preempt-rt
#version: #1 SMP PREEMPT_RT Thu May 6 14:42:12 UTC 2021
#machine: x86_64
#processor: x86_64
#    0:  11th Gen Intel(R) Core(TM) i7-1185GRE @ 2.80GHz
#    1:  11th Gen Intel(R) Core(TM) i7-1185GRE @ 2.80GHz
#    2:  11th Gen Intel(R) Core(TM) i7-1185GRE @ 2.80GHz
#    3:  11th Gen Intel(R) Core(TM) i7-1185GRE @ 2.80GHz
#==============================================================================
#  Test start add stress
#  Test case (1/24): ino_bmark.ctx_msg_posix.no_stress
#..............................................................................
#No stress requested
#
#[663.53]
#ctx_sum is 663.53
#ctx_avg is 663.53
#
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (2/24): ino_bmark.ctx_msg_posix.cpu
#..............................................................................
#Starting stress(cpu)
#  Command: 'taskset -c 0 stress-ng -q -c 4'
#
#[645.61]
#ctx_sum is 645.61
#ctx_avg is 645.61
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (3/24): ino_bmark.ctx_msg_posix.hdd
#..............................................................................
#Starting stress(hdd)
#  Command: 'taskset -c 0 stress-ng -q -d 4 --hdd-bytes 20M'
#
#[674.05]
#ctx_sum is 674.05
#ctx_avg is 674.05
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (4/24): ino_bmark.ctx_msg_posix.io
#..............................................................................
#Starting stress(io)
#  Command: 'taskset -c 0 stress-ng -q -i 4'
#
#[672.7]
#ctx_sum is 672.70
#ctx_avg is 672.70
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (5/24): ino_bmark.ctx_msg_posix.vm
#..............................................................................
#Starting stress(vm)
#  Command: 'taskset -c 0 stress-ng -q -m 4 --vm-bytes 10M'
#
#[680.61]
#ctx_sum is 680.61
#ctx_avg is 680.61
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (6/24): ino_bmark.ctx_msg_posix.full
#..............................................................................
#Starting stress(io+cpu+hdd+vm)
#  Command: 'taskset -c 0 stress-ng -q -i 4 -c 4 -d 4 --hdd-bytes 20M -m 4 --vm-bytes 10M'
#
#[684.91]
#ctx_sum is 684.91
#ctx_avg is 684.91
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (7/24): ino_bmark.deadlock_posix.no_stress
#..............................................................................
#No stress requested
#
#[3185.626667]
#dead_sum is 3185.626667
#dead_avg is 3185.626667
#
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (8/24): ino_bmark.deadlock_posix.cpu
#..............................................................................
#Starting stress(cpu)
#  Command: 'taskset -c 0 stress-ng -q -c 4'
#
#[3292.65]
#dead_sum is 3292.650000
#dead_avg is 3292.650000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (9/24): ino_bmark.deadlock_posix.hdd
#..............................................................................
#Starting stress(hdd)
#  Command: 'taskset -c 0 stress-ng -q -d 4 --hdd-bytes 20M'
#
#[3304.813333]
#dead_sum is 3304.813333
#dead_avg is 3304.813333
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (10/24): ino_bmark.deadlock_posix.io
#..............................................................................
#Starting stress(io)
#  Command: 'taskset -c 0 stress-ng -q -i 4'
#
#[2981.87]
#dead_sum is 2981.870000
#dead_avg is 2981.870000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (11/24): ino_bmark.deadlock_posix.vm
#..............................................................................
#Starting stress(vm)
#  Command: 'taskset -c 0 stress-ng -q -m 4 --vm-bytes 10M'
#
#[3220.873333]
#dead_sum is 3220.873333
#dead_avg is 3220.873333
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (12/24): ino_bmark.deadlock_posix.full
#..............................................................................
#Starting stress(io+cpu+hdd+vm)
#  Command: 'taskset -c 0 stress-ng -q -i 4 -c 4 -d 4 --hdd-bytes 20M -m 4 --vm-bytes 10M'
#
#[3018.213333]
#dead_sum is 3018.213333
#dead_avg is 3018.213333
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (13/24): ino_bmark.preempt_posix.no_stress
#..............................................................................
#No stress requested
#
#[3066.005]
#pree_sum is 3066.005000
#pree_avg is 3066.005000
#
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (14/24): ino_bmark.preempt_posix.cpu
#..............................................................................
#Starting stress(cpu)
#  Command: 'taskset -c 0 stress-ng -q -c 4'
#
#[3010.2]
#pree_sum is 3010.200000
#pree_avg is 3010.200000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (15/24): ino_bmark.preempt_posix.hdd
#..............................................................................
#Starting stress(hdd)
#  Command: 'taskset -c 0 stress-ng -q -d 4 --hdd-bytes 20M'
#
#[3164.07]
#pree_sum is 3164.070000
#pree_avg is 3164.070000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (16/24): ino_bmark.preempt_posix.io
#..............................................................................
#Starting stress(io)
#  Command: 'taskset -c 0 stress-ng -q -i 4'
#
#[3010.33]
#pree_sum is 3010.330000
#pree_avg is 3010.330000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (17/24): ino_bmark.preempt_posix.vm
#..............................................................................
#Starting stress(vm)
#  Command: 'taskset -c 0 stress-ng -q -m 4 --vm-bytes 10M'
#
#[3279.21]
#pree_sum is 3279.210000
#pree_avg is 3279.210000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (18/24): ino_bmark.preempt_posix.full
#..............................................................................
#Starting stress(io+cpu+hdd+vm)
#  Command: 'taskset -c 0 stress-ng -q -i 4 -c 4 -d 4 --hdd-bytes 20M -m 4 --vm-bytes 10M'
#
#[3414.14]
#pree_sum is 3414.140000
#pree_avg is 3414.140000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (19/24): ino_bmark.semaphore_posix.no_stress
#..............................................................................
#No stress requested
#
#[2010.73]
#sem_sum is 2010.730000
#sem_avg is 2010.730000
#
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (20/24): ino_bmark.semaphore_posix.cpu
#..............................................................................
#Starting stress(cpu)
#  Command: 'taskset -c 0 stress-ng -q -c 4'
#
#[2014.075]
#sem_sum is 2014.075000
#sem_avg is 2014.075000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (21/24): ino_bmark.semaphore_posix.hdd
#..............................................................................
#Starting stress(hdd)
#  Command: 'taskset -c 0 stress-ng -q -d 4 --hdd-bytes 20M'
#
#[3242.38]
#sem_sum is 3242.380000
#sem_avg is 3242.380000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (22/24): ino_bmark.semaphore_posix.io
#..............................................................................
#Starting stress(io)
#  Command: 'taskset -c 0 stress-ng -q -i 4'
#
#[2478.045]
#sem_sum is 2478.045000
#sem_avg is 2478.045000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (23/24): ino_bmark.semaphore_posix.vm
#..............................................................................
#Starting stress(vm)
#  Command: 'taskset -c 0 stress-ng -q -m 4 --vm-bytes 10M'
#
#[1975.035]
#sem_sum is 1975.035000
#sem_avg is 1975.035000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (24/24): ino_bmark.semaphore_posix.full
#..............................................................................
#Starting stress(io+cpu+hdd+vm)
#  Command: 'taskset -c 0 stress-ng -q -i 4 -c 4 -d 4 --hdd-bytes 20M -m 4 --vm-bytes 10M'
#
#[2141.185]
#sem_sum is 2141.185000
#sem_avg is 2141.185000
#
#Terminated stress
#Test End

Karbon 700 Core i7-9700TE - Rhealstone

Click to toggle results

#node: ecs-intel-55f8
#release: 5.4.115-rt57-intel-pk-preempt-rt
#version: #1 SMP PREEMPT_RT Thu May 6 14:42:12 UTC 2021
#machine: x86_64
#processor: x86_64
#    0:  Intel(R) Core(TM) i7-9700TE CPU @ 1.80GHz
#    1:  Intel(R) Core(TM) i7-9700TE CPU @ 1.80GHz
#    2:  Intel(R) Core(TM) i7-9700TE CPU @ 1.80GHz
#    3:  Intel(R) Core(TM) i7-9700TE CPU @ 1.80GHz
#    4:  Intel(R) Core(TM) i7-9700TE CPU @ 1.80GHz
#    5:  Intel(R) Core(TM) i7-9700TE CPU @ 1.80GHz
#    6:  Intel(R) Core(TM) i7-9700TE CPU @ 1.80GHz
#    7:  Intel(R) Core(TM) i7-9700TE CPU @ 1.80GHz
#==============================================================================
#  Test start add stress
#  Test case (1/24): ino_bmark.ctx_msg_posix.no_stress
#..............................................................................
#No stress requested
#
#[590.49]
#ctx_sum is 590.49
#ctx_avg is 590.49
#
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (2/24): ino_bmark.ctx_msg_posix.cpu
#..............................................................................
#Starting stress(cpu)
#  Command: 'taskset -c 0 stress-ng -q -c 8'
#
#[605.37]
#ctx_sum is 605.37
#ctx_avg is 605.37
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (3/24): ino_bmark.ctx_msg_posix.hdd
#..............................................................................
#Starting stress(hdd)
#  Command: 'taskset -c 0 stress-ng -q -d 8 --hdd-bytes 20M'
#
#[584.3]
#ctx_sum is 584.30
#ctx_avg is 584.30
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (4/24): ino_bmark.ctx_msg_posix.io
#..............................................................................
#Starting stress(io)
#  Command: 'taskset -c 0 stress-ng -q -i 8'
#
#[590.39]
#ctx_sum is 590.39
#ctx_avg is 590.39
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (5/24): ino_bmark.ctx_msg_posix.vm
#..............................................................................
#Starting stress(vm)
#  Command: 'taskset -c 0 stress-ng -q -m 8 --vm-bytes 10M'
#
#[608.95]
#ctx_sum is 608.95
#ctx_avg is 608.95
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (6/24): ino_bmark.ctx_msg_posix.full
#..............................................................................
#Starting stress(io+cpu+hdd+vm)
#  Command: 'taskset -c 0 stress-ng -q -i 8 -c 8 -d 8 --hdd-bytes 20M -m 8 --vm-bytes 10M'
#
#[594.96]
#ctx_sum is 594.96
#ctx_avg is 594.96
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (7/24): ino_bmark.deadlock_posix.no_stress
#..............................................................................
#No stress requested
#
#[2979.02]
#dead_sum is 2979.020000
#dead_avg is 2979.020000
#
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (8/24): ino_bmark.deadlock_posix.cpu
#..............................................................................
#Starting stress(cpu)
#  Command: 'taskset -c 0 stress-ng -q -c 8'
#
#[3002.426667]
#dead_sum is 3002.426667
#dead_avg is 3002.426667
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (9/24): ino_bmark.deadlock_posix.hdd
#..............................................................................
#Starting stress(hdd)
#  Command: 'taskset -c 0 stress-ng -q -d 8 --hdd-bytes 20M'
#
#[2994.356667]
#dead_sum is 2994.356667
#dead_avg is 2994.356667
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (10/24): ino_bmark.deadlock_posix.io
#..............................................................................
#Starting stress(io)
#  Command: 'taskset -c 0 stress-ng -q -i 8'
#
#[3085.363333]
#dead_sum is 3085.363333
#dead_avg is 3085.363333
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (11/24): ino_bmark.deadlock_posix.vm
#..............................................................................
#Starting stress(vm)
#  Command: 'taskset -c 0 stress-ng -q -m 8 --vm-bytes 10M'
#
#[3016.333333]
#dead_sum is 3016.333333
#dead_avg is 3016.333333
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (12/24): ino_bmark.deadlock_posix.full
#..............................................................................
#Starting stress(io+cpu+hdd+vm)
#  Command: 'taskset -c 0 stress-ng -q -i 8 -c 8 -d 8 --hdd-bytes 20M -m 8 --vm-bytes 10M'
#
#[2949.343333]
#dead_sum is 2949.343333
#dead_avg is 2949.343333
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (13/24): ino_bmark.preempt_posix.no_stress
#..............................................................................
#No stress requested
#
#[2853.805]
#pree_sum is 2853.805000
#pree_avg is 2853.805000
#
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (14/24): ino_bmark.preempt_posix.cpu
#..............................................................................
#Starting stress(cpu)
#  Command: 'taskset -c 0 stress-ng -q -c 8'
#
#[2811.295]
#pree_sum is 2811.295000
#pree_avg is 2811.295000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (15/24): ino_bmark.preempt_posix.hdd
#..............................................................................
#Starting stress(hdd)
#  Command: 'taskset -c 0 stress-ng -q -d 8 --hdd-bytes 20M'
#
#[2832.66]
#pree_sum is 2832.660000
#pree_avg is 2832.660000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (16/24): ino_bmark.preempt_posix.io
#..............................................................................
#Starting stress(io)
#  Command: 'taskset -c 0 stress-ng -q -i 8'
#
#[2846.37]
#pree_sum is 2846.370000
#pree_avg is 2846.370000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (17/24): ino_bmark.preempt_posix.vm
#..............................................................................
#Starting stress(vm)
#  Command: 'taskset -c 0 stress-ng -q -m 8 --vm-bytes 10M'
#
#[2818.59]
#pree_sum is 2818.590000
#pree_avg is 2818.590000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (18/24): ino_bmark.preempt_posix.full
#..............................................................................
#Starting stress(io+cpu+hdd+vm)
#  Command: 'taskset -c 0 stress-ng -q -i 8 -c 8 -d 8 --hdd-bytes 20M -m 8 --vm-bytes 10M'
#
#[2810.305]
#pree_sum is 2810.305000
#pree_avg is 2810.305000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (19/24): ino_bmark.semaphore_posix.no_stress
#..............................................................................
#No stress requested
#
#[1865.975]
#sem_sum is 1865.975000
#sem_avg is 1865.975000
#
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (20/24): ino_bmark.semaphore_posix.cpu
#..............................................................................
#Starting stress(cpu)
#  Command: 'taskset -c 0 stress-ng -q -c 8'
#
#[1824.1]
#sem_sum is 1824.100000
#sem_avg is 1824.100000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (21/24): ino_bmark.semaphore_posix.hdd
#..............................................................................
#Starting stress(hdd)
#  Command: 'taskset -c 0 stress-ng -q -d 8 --hdd-bytes 20M'
#
#[1811.88]
#sem_sum is 1811.880000
#sem_avg is 1811.880000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (22/24): ino_bmark.semaphore_posix.io
#..............................................................................
#Starting stress(io)
#  Command: 'taskset -c 0 stress-ng -q -i 8'
#
#[1875.215]
#sem_sum is 1875.215000
#sem_avg is 1875.215000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (23/24): ino_bmark.semaphore_posix.vm
#..............................................................................
#Starting stress(vm)
#  Command: 'taskset -c 0 stress-ng -q -m 8 --vm-bytes 10M'
#
#[1836.59]
#sem_sum is 1836.590000
#sem_avg is 1836.590000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (24/24): ino_bmark.semaphore_posix.full
#..............................................................................
#Starting stress(io+cpu+hdd+vm)
#  Command: 'taskset -c 0 stress-ng -q -i 8 -c 8 -d 8 --hdd-bytes 20M -m 8 --vm-bytes 10M'
#
#[2215.31]
#sem_sum is 2215.310000
#sem_avg is 2215.310000
#
#Terminated stress
#Test End

TGL-RVP Core i7-1185GRE - Rhealstone

Click to toggle results

#node: ecs-intel-3435
#release: 5.4.115-rt57-intel-pk-preempt-rt
#version: #1 SMP PREEMPT_RT Thu May 6 14:42:12 UTC 2021
#machine: x86_64
#processor: x86_64
#    0:  11th Gen Intel(R) Core(TM) i7-1185GRE @ 2.80GHz
#    1:  11th Gen Intel(R) Core(TM) i7-1185GRE @ 2.80GHz
#    2:  11th Gen Intel(R) Core(TM) i7-1185GRE @ 2.80GHz
#    3:  11th Gen Intel(R) Core(TM) i7-1185GRE @ 2.80GHz
#==============================================================================
#  Test start add stress
#  Test case (1/24): ino_bmark.ctx_msg_posix.no_stress
#..............................................................................
#No stress requested
#
#[690.24]
#ctx_sum is 690.24
#ctx_avg is 690.24
#
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (2/24): ino_bmark.ctx_msg_posix.cpu
#..............................................................................
#Starting stress(cpu)
#  Command: 'taskset -c 0 stress-ng -q -c 4'
#
#[687.16]
#ctx_sum is 687.16
#ctx_avg is 687.16
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (3/24): ino_bmark.ctx_msg_posix.hdd
#..............................................................................
#Starting stress(hdd)
#  Command: 'taskset -c 0 stress-ng -q -d 4 --hdd-bytes 20M'
#
#[712.08]
#ctx_sum is 712.08
#ctx_avg is 712.08
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (4/24): ino_bmark.ctx_msg_posix.io
#..............................................................................
#Starting stress(io)
#  Command: 'taskset -c 0 stress-ng -q -i 4'
#
#[677.34]
#ctx_sum is 677.34
#ctx_avg is 677.34
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (5/24): ino_bmark.ctx_msg_posix.vm
#..............................................................................
#Starting stress(vm)
#  Command: 'taskset -c 0 stress-ng -q -m 4 --vm-bytes 10M'
#
#[703.52]
#ctx_sum is 703.52
#ctx_avg is 703.52
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (6/24): ino_bmark.ctx_msg_posix.full
#..............................................................................
#Starting stress(io+cpu+hdd+vm)
#  Command: 'taskset -c 0 stress-ng -q -i 4 -c 4 -d 4 --hdd-bytes 20M -m 4 --vm-bytes 10M'
#
#[701.52]
#ctx_sum is 701.52
#ctx_avg is 701.52
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (7/24): ino_bmark.deadlock_posix.no_stress
#..............................................................................
#No stress requested
#
#[3275.633333]
#dead_sum is 3275.633333
#dead_avg is 3275.633333
#
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (8/24): ino_bmark.deadlock_posix.cpu
#..............................................................................
#Starting stress(cpu)
#  Command: 'taskset -c 0 stress-ng -q -c 4'
#
#[3231.73]
#dead_sum is 3231.730000
#dead_avg is 3231.730000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (9/24): ino_bmark.deadlock_posix.hdd
#..............................................................................
#Starting stress(hdd)
#  Command: 'taskset -c 0 stress-ng -q -d 4 --hdd-bytes 20M'
#
#[3039.293333]
#dead_sum is 3039.293333
#dead_avg is 3039.293333
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (10/24): ino_bmark.deadlock_posix.io
#..............................................................................
#Starting stress(io)
#  Command: 'taskset -c 0 stress-ng -q -i 4'
#
#[3496.99]
#dead_sum is 3496.990000
#dead_avg is 3496.990000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (11/24): ino_bmark.deadlock_posix.vm
#..............................................................................
#Starting stress(vm)
#  Command: 'taskset -c 0 stress-ng -q -m 4 --vm-bytes 10M'
#
#[3108.073333]
#dead_sum is 3108.073333
#dead_avg is 3108.073333
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (12/24): ino_bmark.deadlock_posix.full
#..............................................................................
#Starting stress(io+cpu+hdd+vm)
#  Command: 'taskset -c 0 stress-ng -q -i 4 -c 4 -d 4 --hdd-bytes 20M -m 4 --vm-bytes 10M'
#
#[3268.083333]
#dead_sum is 3268.083333
#dead_avg is 3268.083333
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (13/24): ino_bmark.preempt_posix.no_stress
#..............................................................................
#No stress requested
#
#[3077.255]
#pree_sum is 3077.255000
#pree_avg is 3077.255000
#
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (14/24): ino_bmark.preempt_posix.cpu
#..............................................................................
#Starting stress(cpu)
#  Command: 'taskset -c 0 stress-ng -q -c 4'
#
#[3051.04]
#pree_sum is 3051.040000
#pree_avg is 3051.040000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (15/24): ino_bmark.preempt_posix.hdd
#..............................................................................
#Starting stress(hdd)
#  Command: 'taskset -c 0 stress-ng -q -d 4 --hdd-bytes 20M'
#
#[3264.9]
#pree_sum is 3264.900000
#pree_avg is 3264.900000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (16/24): ino_bmark.preempt_posix.io
#..............................................................................
#Starting stress(io)
#  Command: 'taskset -c 0 stress-ng -q -i 4'
#
#[3091.07]
#pree_sum is 3091.070000
#pree_avg is 3091.070000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (17/24): ino_bmark.preempt_posix.vm
#..............................................................................
#Starting stress(vm)
#  Command: 'taskset -c 0 stress-ng -q -m 4 --vm-bytes 10M'
#
#[3159.005]
#pree_sum is 3159.005000
#pree_avg is 3159.005000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (18/24): ino_bmark.preempt_posix.full
#..............................................................................
#Starting stress(io+cpu+hdd+vm)
#  Command: 'taskset -c 0 stress-ng -q -i 4 -c 4 -d 4 --hdd-bytes 20M -m 4 --vm-bytes 10M'
#
#[3473.495]
#pree_sum is 3473.495000
#pree_avg is 3473.495000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (19/24): ino_bmark.semaphore_posix.no_stress
#..............................................................................
#No stress requested
#
#[1997.905]
#sem_sum is 1997.905000
#sem_avg is 1997.905000
#
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (20/24): ino_bmark.semaphore_posix.cpu
#..............................................................................
#Starting stress(cpu)
#  Command: 'taskset -c 0 stress-ng -q -c 4'
#
#[2017.175]
#sem_sum is 2017.175000
#sem_avg is 2017.175000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (21/24): ino_bmark.semaphore_posix.hdd
#..............................................................................
#Starting stress(hdd)
#  Command: 'taskset -c 0 stress-ng -q -d 4 --hdd-bytes 20M'
#
#[1509.205]
#sem_sum is 1509.205000
#sem_avg is 1509.205000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (22/24): ino_bmark.semaphore_posix.io
#..............................................................................
#Starting stress(io)
#  Command: 'taskset -c 0 stress-ng -q -i 4'
#
#[1899.175]
#sem_sum is 1899.175000
#sem_avg is 1899.175000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (23/24): ino_bmark.semaphore_posix.vm
#..............................................................................
#Starting stress(vm)
#  Command: 'taskset -c 0 stress-ng -q -m 4 --vm-bytes 10M'
#
#[1980.015]
#sem_sum is 1980.015000
#sem_avg is 1980.015000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (24/24): ino_bmark.semaphore_posix.full
#..............................................................................
#Starting stress(io+cpu+hdd+vm)
#  Command: 'taskset -c 0 stress-ng -q -i 4 -c 4 -d 4 --hdd-bytes 20M -m 4 --vm-bytes 10M'
#
#[2145.63]
#sem_sum is 2145.630000
#sem_avg is 2145.630000
#
#Terminated stress
#Test End

EHL-CRB Atom x6425RE - Rhealstone

Click to toggle results

#node: ecs-intel-0046
#release: 5.4.115-rt57-intel-pk-preempt-rt
#version: #1 SMP PREEMPT_RT Thu May 6 14:42:12 UTC 2021
#machine: x86_64
#processor: x86_64
#    0:  Intel Atom(R) Processor x6425RE @ 1.90GHz
#    1:  Intel Atom(R) Processor x6425RE @ 1.90GHz
#    2:  Intel Atom(R) Processor x6425RE @ 1.90GHz
#    3:  Intel Atom(R) Processor x6425RE @ 1.90GHz
#==============================================================================
#  Test start add stress
#  Test case (1/24): ino_bmark.ctx_msg_posix.no_stress
#..............................................................................
#No stress requested
#
#[1412.93]
#ctx_sum is 1412.93
#ctx_avg is 1412.93
#
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (2/24): ino_bmark.ctx_msg_posix.cpu
#..............................................................................
#Starting stress(cpu)
#  Command: 'taskset -c 0 stress-ng -q -c 4'
#
#[1423.62]
#ctx_sum is 1423.62
#ctx_avg is 1423.62
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (3/24): ino_bmark.ctx_msg_posix.hdd
#..............................................................................
#Starting stress(hdd)
#  Command: 'taskset -c 0 stress-ng -q -d 4 --hdd-bytes 20M'
#
#[1422.65]
#ctx_sum is 1422.65
#ctx_avg is 1422.65
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (4/24): ino_bmark.ctx_msg_posix.io
#..............................................................................
#Starting stress(io)
#  Command: 'taskset -c 0 stress-ng -q -i 4'
#
#[1446.35]
#ctx_sum is 1446.35
#ctx_avg is 1446.35
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (5/24): ino_bmark.ctx_msg_posix.vm
#..............................................................................
#Starting stress(vm)
#  Command: 'taskset -c 0 stress-ng -q -m 4 --vm-bytes 10M'
#
#[1635.92]
#ctx_sum is 1635.92
#ctx_avg is 1635.92
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (6/24): ino_bmark.ctx_msg_posix.full
#..............................................................................
#Starting stress(io+cpu+hdd+vm)
#  Command: 'taskset -c 0 stress-ng -q -i 4 -c 4 -d 4 --hdd-bytes 20M -m 4 --vm-bytes 10M'
#
#[1528.82]
#ctx_sum is 1528.82
#ctx_avg is 1528.82
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (7/24): ino_bmark.deadlock_posix.no_stress
#..............................................................................
#No stress requested
#
#[6250.596667]
#dead_sum is 6250.596667
#dead_avg is 6250.596667
#
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (8/24): ino_bmark.deadlock_posix.cpu
#..............................................................................
#Starting stress(cpu)
#  Command: 'taskset -c 0 stress-ng -q -c 4'
#
#[6054.156667]
#dead_sum is 6054.156667
#dead_avg is 6054.156667
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (9/24): ino_bmark.deadlock_posix.hdd
#..............................................................................
#Starting stress(hdd)
#  Command: 'taskset -c 0 stress-ng -q -d 4 --hdd-bytes 20M'
#
#[6183.6]
#dead_sum is 6183.600000
#dead_avg is 6183.600000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (10/24): ino_bmark.deadlock_posix.io
#..............................................................................
#Starting stress(io)
#  Command: 'taskset -c 0 stress-ng -q -i 4'
#
#[6378.04]
#dead_sum is 6378.040000
#dead_avg is 6378.040000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (11/24): ino_bmark.deadlock_posix.vm
#..............................................................................
#Starting stress(vm)
#  Command: 'taskset -c 0 stress-ng -q -m 4 --vm-bytes 10M'
#
#[6049.556667]
#dead_sum is 6049.556667
#dead_avg is 6049.556667
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (12/24): ino_bmark.deadlock_posix.full
#..............................................................................
#Starting stress(io+cpu+hdd+vm)
#  Command: 'taskset -c 0 stress-ng -q -i 4 -c 4 -d 4 --hdd-bytes 20M -m 4 --vm-bytes 10M'
#
#[5643.946667]
#dead_sum is 5643.946667
#dead_avg is 5643.946667
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (13/24): ino_bmark.preempt_posix.no_stress
#..............................................................................
#No stress requested
#
#[6185.19]
#pree_sum is 6185.190000
#pree_avg is 6185.190000
#
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (14/24): ino_bmark.preempt_posix.cpu
#..............................................................................
#Starting stress(cpu)
#  Command: 'taskset -c 0 stress-ng -q -c 4'
#
#[6144.92]
#pree_sum is 6144.920000
#pree_avg is 6144.920000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (15/24): ino_bmark.preempt_posix.hdd
#..............................................................................
#Starting stress(hdd)
#  Command: 'taskset -c 0 stress-ng -q -d 4 --hdd-bytes 20M'
#
#[6091.94]
#pree_sum is 6091.940000
#pree_avg is 6091.940000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (16/24): ino_bmark.preempt_posix.io
#..............................................................................
#Starting stress(io)
#  Command: 'taskset -c 0 stress-ng -q -i 4'
#
#[6283.465]
#pree_sum is 6283.465000
#pree_avg is 6283.465000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (17/24): ino_bmark.preempt_posix.vm
#..............................................................................
#Starting stress(vm)
#  Command: 'taskset -c 0 stress-ng -q -m 4 --vm-bytes 10M'
#
#[8231.88]
#pree_sum is 8231.880000
#pree_avg is 8231.880000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (18/24): ino_bmark.preempt_posix.full
#..............................................................................
#Starting stress(io+cpu+hdd+vm)
#  Command: 'taskset -c 0 stress-ng -q -i 4 -c 4 -d 4 --hdd-bytes 20M -m 4 --vm-bytes 10M'
#
#[7674.265]
#pree_sum is 7674.265000
#pree_avg is 7674.265000
#
#Terminated stress
#Test End
#
#==============================================================================
#  Test start add stress
#  Test case (19/24): ino_bmark.semaphore_posix.no_stress
#..............................................................................
#No stress requested
#
#[4027.46]
#sem_sum is 4027.460000
#sem_avg is 4027.460000
#
#Test End

MMIO-Latency Results

See also

See section MMIO Latency for more information about this benchmark.

The following configuration was used:

• Configure non-RT related tasks to core 0

Vecow Core i7-8665UE - MMIO-Latency

Click to toggle results

  RT Core Module
------------------------
Stats:
max= 7854
avg= 3394
min= 571
total= 99746301
loops= 29384

mmio-outliers: 29287
sched-outliers: 3
Floating Max:
Index: 8141  Max: 7854

Maxtang Core i7-8665U - MMIO-Latency

Click to toggle results

     RT Core Module
------------------------
Stats:
 max= 4851
 avg= 3314
 min= 705
 total= 98342350
 loops= 29666

mmio-outliers: 29660
sched-outliers: 0
Floating Max:
 Index: 19748      Max: 4851

Vecow Core i7-1185G7E - MMIO-Latency

Click to toggle results

   RT Core Module
------------------------
Stats:
max= 10044
avg= 4290
min= 684
total= 126548622
loops= 29492

mmio-outliers: 29466
sched-outliers: 12
Floating Max:
Index: 1945     Max: 10044

Karbon 700 Core i7-9700TE - MMIO-Latency

Click to toggle results

  RT Core Module
------------------------
Stats:
max= 14892
avg= 5814
min= 2111
total= 171457266
loops= 29487

mmio-outliers: 29343
sched-outliers: 138
Floating Max:
Index: 21410         Max: 14892

TGL-RVP Core i7-1185GRE - MMIO-Latency

Click to toggle results

   RT Core Module
------------------------
Stats:
max= 5501
avg= 133
min= 117
total= 3927813
loops= 29503

mmio-outliers: 10
sched-outliers: 0
Floating Max:
Index: 27337         Max: 5501